【正文】 or C2 is charged positively via D2 to 168 V. The total voltage across C1 and C2 in series is then 336 V. It can be seen in Figure that with either transistor “on,” the “off” transistor is subjected to the maximum DC input voltage and not twice that value. Since the topology subjects the “off” transistor to only Vdc and not 2Vdc, there are many inexpensive bipolar and MOSFET transistors that can support the nominal 336 DC V plus 15% upper maximum of 386 V. Thus the equipment can be used with either 120 or 220V AC line inputs by making a simple switch or linkage change. Assuming a nominal rectified DC voltage of 336 V, the topology works as follows: For the moment, ignore the small series blocking capacitor Cb . Assume the bottom end of Np is connected to the junction of C1 and C2. Then if the leakages in C1, C2 are assumed to be equal, that point will be at half the rectified DC voltage, about 168 V. It is generally good practice to place equal bleeder resistors across C1 and C2 to equalize their voltage drops. Now Q1 and Q2 conduct on alternate half cycles. When Q1 is “on” and Q2 “off” (Figure ), the dot end of Np is 168 V positive with respect to its nodot end, and the “off” stress on Q2 is only 336 V. When Q2 is “on” and Q1 “off,” the dot end of Np is 168 V negative with respect to its nodot end and the emitter of Q1 is 336 V negative with respect to its collector. This AC squarewave primary voltage produces fullwave square Waveshapes on all secondaries—exactly like the secondary voltages in the pushpull topology. The selection of secondary voltages and wire sizes and the output inductor and capacitor proceed exactly as for the pushpull circuit. HalfBridge Magics Selecting Maximum “ On” Time, Magic Core, and Primary Turns It can be seen in Figure , that if Q1 and Q2 are “on” simultaneously—even for a very short time—there is a short circuit across the supply voltage and the transistors will be destroyed. To make sure that this does not happen, the maximum Q1 or Q2 “on” time, which occurs at minimum DC supply voltage, will be set at 80% of a half period. The secondary turns will be chosen so that the desired output voltages are obtained with an “on” time of no more than “on”time clamp will be provided to ensure that the “on” time can never be greater than The core is selected from the tables in Chapter 7 mentioned earlier. These tables give maximum available output power as a function of operating frequency, peak flux density, core and iron areas, and coil current density. With a core selected and its iron area known, the number of primary turns is calculated from Faraday’s law (Eq. ) using the minimum primary voltage (Vdc/2) ? 1, and the maximum “on” time of , the flux excursion dB in the equation is twice the desired peak flux density (1600 G below 50 kHz, or less at higher frequency), because the halfbridge core operates in the first and third quadrants of its hysteresis loop—unlike the forward converter (Section ), which operates in the first quadrant only. The Relation Between Input Voltage,