【正文】 ue. The approach is straightforward, but is being increasingly tortuous as designs bee more plicated and the number of possible test vectors mushrooms. So recently, electronic design automation panies have been turning to model checking to prove that designs are correctly done. The sticking point with model checking is its great difficulty of use. It is not for most engineers, said Simon Napper, chief operating officer OF Innologic Systems Inc., San Jose, Calif. The usage model is very difficultit checks properties. But the designer isn39。s ranch of six strivers from Sun Microsystems. The pany has teamed up with National Semiconductor Corp, Santa Clara, Calif., to provide this service for National39。 您說 superlog？ 芯片系統(tǒng)由電路和軟件組成運行。 在成立這個蒸蒸日上的企業(yè)前，合作者，現(xiàn)經(jīng)營主任 simon davidmann 和 peter flake 已經(jīng)得出了為滿足片上系統(tǒng)發(fā)展現(xiàn)有語言的實用性?！边@時用比特和 VHDL語言與 Java 語言將其連接起來。其中 magma 設(shè)計自動化公司， sente 公司和 viewlogic 公司將發(fā)展建立的 superlog 上的工具。它將是一種標(biāo)準(zhǔn)語言使半導(dǎo)體供應(yīng)商， IP 供應(yīng)商和系統(tǒng)房屋可交換系統(tǒng)級 IP和可執(zhí)行規(guī)格，并且電子設(shè)計自動化工業(yè)能夠發(fā)明一種編寫互用性的工具。 然而，問題依然存在。據(jù)推測，如果這個陣列按計劃工作，則最終芯片也將工作。這些現(xiàn)場可編程門陣列以 100 兆赫運行，擁有超過一百萬門。第一是分開或打破ASIC 寄存器傳送級編碼，使之成為不同的現(xiàn)場可編程門陣列。因此最近電子設(shè)計自動化公司已經(jīng)運用模型檢驗法去驗證設(shè)計是否正確。為了說明和完全檢驗一個四位微機芯片的加法器，需要 256 個二元向量，運行 256 個模擬周期?！? innologic 公司已經(jīng)發(fā)行了兩個版本的象征性模擬。由于在一起更為緊密，必須控制連接體之間的串?dāng)_。 對于位于加州 cupertino 的正在開發(fā) Blast Fusion 結(jié)構(gòu)設(shè)計系統(tǒng)的 Magma 設(shè)計自動化公司來說，時序收斂是重中之重。 關(guān)注加州 Milpitas 的 是對有用信息的提取，從提供者的網(wǎng)址上我們可以看到關(guān)于集成電路，芯片和電路板的信息。公司的產(chǎn)品包括 quickdata 服務(wù)器和 quickdata 轉(zhuǎn)換器。（ meeting 是一項微軟產(chǎn)品，可以完成對計算機桌面的遠(yuǎn)程共享）。用戶只需要一個網(wǎng)絡(luò)瀏覽器，其余均不需要。 該公司已經(jīng)同加州圣克拉拉的 semiconductor 公司建立團隊合作關(guān) 系，以為全球消費者提供此項服務(wù)。不過也坐落在俄勒岡波特蘭市的 transim 公司已經(jīng)在基于網(wǎng)絡(luò)的設(shè)計工具上跨越了一大步。 俄勒岡波特蘭市的 genedax 公司的任務(wù)便是運用網(wǎng)絡(luò)增強設(shè)計者的能力，以創(chuàng)造和管理大型而復(fù)雜的設(shè)計，提高設(shè)計的再利用率，拓寬智力性能的途徑。他說“簡而言之，人們過去用幾周的時間去得到數(shù)據(jù)單表?；旧险f，這種方法首先確定時序，然后調(diào)整信元大小以滿足時間的需要。 由加州 Sunnyvale 的 monterey設(shè)計系統(tǒng)公司提出的方案稱為全球設(shè)計技術(shù)。 EXPCV則意在用戶定制設(shè)計和存儲塊。 象征性模擬能完全檢驗的電路，僅使用正規(guī)檢驗的話對其復(fù)雜性有限制。加州圣荷西 innologic系統(tǒng)公司操作部經(jīng)理 simon napper 說“并非大多數(shù)工程師能夠使用它。此時做時間分析。將九個這樣的芯片以 3 3 陣列放置在板上，設(shè)計者可以描述高達(dá) 百萬的ASIC 門。 然而走勢很緩慢。但據(jù) KUNEL說， system C 的合成工具將在用戶群體中得出一個語言上被廣泛接受的自然結(jié)果。 kunkel告訴 IEEE spectrum說大部分軟件開發(fā)者用 C++且系統(tǒng)開發(fā)者已經(jīng)運用 C++在行為級上描述他們的系統(tǒng)。 沖向終點的比賽 并不是每一個 人都相信我們需要新的語言。從 C 和Java 方面 superlog又集成了動態(tài)處理器和其他軟件編制。 davidmann 說一種設(shè)計語言必須滿足三個需求。通常，芯片的功能被寫在紙上后，硬件部件就交給了集成電路設(shè)計者，軟件部件就給了程序設(shè)計者，在以后的某個閘門在合起來組在一起。首先就是缺乏一些東西即設(shè)計的硬件部件與軟件部件之間缺少統(tǒng)一的語言。XV verifies designs written in Virology. EXPCV is meant for custom designs and memory blocks. THE TIME IS RIGHT Though the design of ICs with semiconductor geometries below pm face challenges throughout development, some of the biggest hurdles occur during physical design, when the gates are placed on the chip and the interconnects are routed between them Problems occur here for a number of reasons. First, the capacitance, resistance, and inductance of the interconnects cannot be ignored, as they were in older, larger technologies. Crosstalk between interconnects。VHDL language。s functionality is spelled out, usually on paper, the hardware potent is handed off to the circuit designers and the software is given to the pro grammars, to meet up again at some later date. The part of the chips functionality that will end up as logic gates and transistors is writ ten in a hardware design languageVirology or VHDL, while the part that will end up as software is most often described in the programming language C or C++. The use of these disparate languages hampers the ability to describe, model, and debug the circuitry of the IC and the software in a coherent fashion. It is time, many in the industry believe, for a new design language that can cope with both hardware and software from the initial design specification right through to final verification. Just such a new language has been developed by CoDesign Automation Inc., San Jose, Calif. Before launching such an ambitious enterprise, cofounders Simon Davidmann, who is also chief operating officer, and Peter Flake ruled out the usefulness of extending an existing language to meet systemonchip needs. Among the candidates for extension were C, C++, Java, and Verilog. A design language should satisfy three requirements, maintained Davidmann. It should unify the design process. It should make designing more efficient. And it should evolve out of an existing methodology. None of the existing approaches filled the bill. So Davidmann and Flake set about developing new codesign language called Superlog. A natural starting point was a blend of Virology and C since from an algorithm poi