【正文】 題目： 基于 BURG算法的譜估計研究及 其 MATLAB實現(xiàn) 目 錄 一、畢業(yè)設(shè)計（論文）開題報告 二、畢業(yè)設(shè)計（論文）外文資料翻譯及原文 三、學(xué)生 “畢業(yè)論文（論文）計劃、進(jìn)度、檢查及落實表 ” 四、實習(xí)鑒定表 XX大學(xué) XX學(xué)院 畢業(yè)設(shè)計（論文） 開題報告 題目： 基于 BURG算法的譜估計研究及 其 MATLAB實現(xiàn) 機(jī)電 系 電子信息工程 專業(yè) 學(xué) 號： 學(xué)生姓名： 指導(dǎo)教師： （職稱：講 師 ） （職稱： ） XXXX年 XX月 X日 課題來源 功率譜估計在近 30 年中獲得了飛速發(fā)展?，F(xiàn)代譜分析受算法的復(fù)雜度高和集成電路處理速度的影響，因此在引信系統(tǒng)中的應(yīng)用會受到很大的限制。 20xx 年 1 月 11 日 20xx 年 3 月 5 日： 進(jìn)行畢業(yè)實習(xí)，并 填寫 畢業(yè)實習(xí) 報告。 特色或創(chuàng)新之處 由于經(jīng)典譜估計中將數(shù)據(jù)工作區(qū)外的未知數(shù)據(jù)假設(shè)為零，相當(dāng)于 數(shù)據(jù)加窗，導(dǎo)致其分辨率降低。 for example, operations such as division and squareroot are often necessary. These arithmetic processes exhibit munication bottleneck and their hardware implementation can be inefficient when used in conjunction with multipliers. A programmable, bitserial, multiplier/divider, which overes the bottleneck problems by using a data interleaving scheme, is introduced in this paper. This interleaved processor is used to show how the parametric Modified Covariance spectral estimator can be efficiently routed on a field programmable gate array for realtime applications. 1. INTRODUCTION Due to its ease of hardware and software implementation the shortterm fast Fourier transform(STFFT)is widely used for spectral estimation and is known as the conventional method. However, the technique has drawbacks in terms of spectral resolution and accuracy caused by the finite length of the input data sequence used. Windowing of input data causes spectral broadening and Gibb’s phenomenon of spectral leakage can mask the weaker frequency ponents of the true power spectral density(PSD)[1]. These unwanted effects can be reduced by using longer data sequence lengths, so that the transformed signal bees a better representation of the infinite data sequence, but in real life this usually is not feasible as the characteristics of the input data may change with time. Over short periods of time the data signals can often be assumed to exhibit widesense stationarity, where the signal characteristics are assumed approximately constant but the spectral resolution is therefore limited. In attempts to improve the PSD estimation, windowing functions, Bartlett or Hanning for example, can be used to reduce sidelobe levels but these lower spectral resolution by broadening the main lobe of the PSD[2]. Model based, parametric spectral estimation techniques can alternatively be used, where the unrealistic assumption that data is zero outside the window of interest is dropped[1]. Either knowledge of the underlying process or reasonable assumptions about the nature of the unobserved data are used to improve frequency resolution over the conventional approaches. The putational burden of such processors is however much higher than the STFFT and arithmetic functions such as division and squareroot often bee necessary. In the division and squareroot nonrestoring algorithms there is an inherent dependency that the result bits must be puted in a most significant bit(MSB)first manner, with the putation of a bit directly dependent upon the result of the previous one[3]. This interdependency makes it difficult to efficiently realize such arithmetic functions in hardware, and implementations are usually much slower than other basic functions such as multiplication, addition and subtraction. Communication bottlenecks can therefore easily occur in systolic arrays where different types of processors are interconnected. The difficulties with hardware implementation of parametric spectral estimators have led to a preference of software implementation on homogeneous DSP works[4]. However, high levels of processing capacity have not been fully reflected in system throughput since the increased munication incurred as a result of parallelism is constrained by munication bus performance. This restricts the range of problems that can be puted in realtime and the software approach may sometimes be inadequate for realtime spectral estimation. In this paper, hardware implementation of a parametric spectral estimator is addressed. A bitserial processor capable of division and inner product step putation is developed by bining separate processors for these functions. The design uses a high level of pipelining so that division can be puted at a high rate and multiplication is performed on a MSB first data stream, eliminating the bottleneck problem. The high level of pipelining allows many independent putations to be performed simultaneously or interleaved. The use of the interleaving scheme is demonstrated by implementing the design of a Modified Covariance type of parametric spectral estimator, to produce a field programmable gate array(FPGA)based system for the spectral analysis of Doppler signals from ultrasonic blood flow detectors. 2. MODIFIED COVARIANCE SPECTRAL ESTIMATION The model order p=4 Modified Covariance(MC)spectral estimator, proven to be optimally cost efficient for the blood flow application where mean velocity and flow disturbance are of interest[5], involves solving the following linear system of covariance matrix equations: (1) where each element jiC, is obtained from: ? ??? ??? ????????? 1 1 0, )()1(2 1 N pn pN nji jninjninNC (2) for a window of length N data samples. The ka? filter parameter estimates are obtained by solution of the linear system(1), using the Cholesky, forward elimination and back substitution algorithms. The signal white noise variance estimate, 2?? is calculated as: kpk k cac ,010,02 ?? ??? ??? (3) and the power spectral density(PSD), )(? nMCfP , is obtained from: 21222