【正文】 = read_data_2, MemRead = MemRead, Memwrite = MemWrite, clock = clock, reset = reset )。 Zero_out = Zero。 BEGIN copy important signals to output pins for easy display in Simulator Instruction_out = Instruction。 SIGNAL RegDst STD_LOGIC。 SIGNAL read_data_1 STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 外文翻譯（原文） 8 END COMPONENT。 Function_opcode IN STD_LOGIC_VECTOR( 5 DOWNTO 0 )。 MemWrite OUT STD_LOGIC。 clock, reset IN STD_LOGIC )。 COMPONENT Idecode PORT( read_data_1 OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 ARCHITECTURE structure OF TOP_SPIM IS COMPONENT Ifetch PORT( Instruction OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。Value of memory at address A = Register 4 The MIPS Iformat instruction, BEQ, branches if two registers have the same value. As an example, the instruction BEQ $1, $2, LABEL jumps to LABEL if register 1 equals register 2. A branch instruction‘s address field contains the offset from the current address. The PC must be added to the address field to pute the branch address. This is called PCrelative addressing. LW and SW instructions contain an offset and a base register that are used for array addressing. As an example, LW $1, 100($2) adds an offset of 100 to the contents of register 2 and uses the sum as the memory address to read data from. The value from memory is then loaded into register 1. Using register 0, which always contains a 0, as the base register disables this addressing feature. Table MIPS Processor Core Instructions 外文翻譯（原文） 3 A summary of the basic MIPS instructions is shown in Table . In depth explanations of all MIPS instructions and assembly language programming examples can be found in the references listed in section . A hardware implementation of the MIPS processor core based on the example in the widely used textbook, Computer Organization and Design The HardwareSoftware Interface by Patterson and Hennessy, is shown in Figure . This implementation of the MIPS performs fetch, decode, and execute in one clock cycle. Starting at the left in Figure , the program counter (PC) is used to fetch the next address in instruction memory. Since memory is byte addressable, four is added to address the next 32bit (or 4byte) word in memory. At the same time as the instruction fetch, the adder above instruction memory is used to add four to the PC to generate the ne xt address. The output of instruction memory is the next 32bit instruction. The instruction‘s opcode is then sent to the control unit and the function code is sent to the ALU control unit. The instruction‘s register address fields are used to address the twoport register file. The twoport register file can perform two independent reads and one write in one clock cycle. This implements the decode 外文翻譯（原文） 4 operation. Figure MIPS Single Clock Cycle Implementation The two outputs of the register file then feed into the data ALU inputs. The control units setup the ALU operation required to execute the instruction. Next, Load and Store instructions read or write to data memory. Rformat instructions bypass data memory using a multiplexer. Last, Rformat and Load instructions write back a new value into the register file. PCrelative branch instructions use the adder and multiplexer shown above the data ALU in Figure to pute the branch address. The multiplexer is required for conditional branch operations. After all outputs have stabilized, the next clock loads in the new value of the PC and the process repeats for the next instruction. RISC instruction sets are easier to pipeline. With pipelining, the fetch, decode, execute, data memory, and register file write operations all work in parallel. In a single clock cycle, five different instructions are present in the pipeline. The basis for a pipelined hardware implementation of the MIPS is shown in Figure . 外文翻譯（原文） 5 Additional plications arise because of data dependencies between instructions in the pipeline and branch operations. These problems can be resolved using hazard detection, data forwarding techniques, and branch flushing. With pipelining, most RISC instructions execute in one clock cycle. Branch instructions will still require flushing of the pipeline. Exercises that add pipelining to the processor core are included at the end of the chapter. Figure MIPS Pipelined Implementation Using VHDL to Synthesize the MIPS Processor Core A VHDLsynthesis model of the MIPS single clock cycle model from Figure will be developed in this section. This model can be used for simulation and implemented using the UP3 board. The full 32bit model requires a couple minutes to synthesize. When testing new changes you might want to use the faster functional (. no timing delays) simulation approach before using a full timing delay model. This approach is monly used on larger models with long synthesis and simulation times. A twolevel hierarchy is used in the model. is the toplevel of the hierarchy. It consists of a structural VHDL model that connects the five behavioral modules. The five behavioral modules are already setup so that they correspond to the 外文翻譯（原文） 6 different stages for the MIPS. This makes it much easier to modify when the model is pipelined in later laboratory exercises. For many synthesis tools, hierarchy is also required to synthesize large logic designs. is the VHDL submodule that contains instruction memory and the program counter. contains the logic for the control unit. contains the multiported register file. contains the data and branch address ALUs. contains the data memory. The TopLevel Module The file contains the toplevel design file. is a VHDL structural model that connects the five ponent parts of the MIPS. This module could also be created using the schematic editor and connecting the symbols for each VHDL submodule