【正文】
ee methods to achieve this ? Voltage reduction ? Reversible logic ? Adiabatic switching An Energy Metric for CPUs cont’d ? Voltage Reduction ? E/clock is directly proportional to V2 ? Lowervoltage, slowerclock chip。 less energy per cycle ? Reducing The Energy Consumption ? The same of cycles but lower voltage ? Ex: a task with 100ms deadline ? Method 1 ? 50ms full speed。 undesirable ? Bad response time ? FUTURE (boundeddelay limitedfuture) ? Taking the future trace of a small window ? Window sizes: 1 ms ~ 400 sec ? Impractical but desirable ? Good response time on a window of 10 to 50 ms Scheduling Algorithms cont’d ? PAST (boundeddelay limitedpast) ? Looking a fixed window into the past ? Assuming the next window will be like the previous one ? Examine % busy during the pervious interval and adjust speed for the next interval ? Excess cycles can build up if speed (+voltage) is set too low. = Penalty metric ? Excess Cycle Penalty ? At each interval, count up left over cycles that accumulated because you ran too slow ? Switch to full speed if there were more excess cycles than idle time in the previous interval ? Hard idle (page fault, disk request) cannot be squeezed Trace Driven Simulation ? Trace Points ? Sched: context switch away a process ? Idle on: enter the idle loop ? I