【正文】 or current. The following diagram shows the basic setup of such a system. Unit refers to the input signals used to filter hardware or software. If the filter input, output signals are separated, they are bound to respond to the impact of the Unit is separated, such as digital filters filter definition. Digital filter function, which was to import sequences X transformation into export operations through a series Y. According to figures filter function 24hour live response characteristics, digital filters can be divided into two, namely, unlimited long live long live the corresponding IIR filter and the limited response to FIR filters. IIR filters have the advantage of the digital filter design can use simulation results, and simulation filter design of a large number of tables may facilitate simple. It is the shortings of the nonlinear phase。 Again, the use of FPGA devices can enhance system reliability, reduced maintenance workload, thereby lowering the cost of maintenance services for the system. In short, the use of FPGA devices for system design to save costs. FPGA design principles : FPGA design an important guiding principles : the balance and size and speed of exchange, the principles behind the design of the filter expression of a large number of certification. Here, area means a design exertion FPGA/CPLD logic resources of the FPGA can be used to the typical consumption (FF) and the search table (IUT) to measure more general measure can be used to design logic equivalence occupied by the door is measured. pace means stability operations in the chip design can achieve the highest frequency, the frequency of the time series design situation, and design to meet the clock cycle PADto pad, Clock Setup Time, Clock Hold Beijing, ClocktoOutput Delay, and other characteristics of many time series closely related. Area (area) and speed (speed) runs through the two targets FPGA design always is the ultimate design quality evaluation criteria. On the size and speed of the two basic concepts : balance of size and speed and size and speed of swap. One pair of size and speed is the unity of opposites contradictions body. Requirements for the design of a design while the smallest, highest frequency of operation is unrealistic. More scientific goal should be to meet the design requirements of the design time series (includes requirements for the design frequency) premise, the smallest chip area occupied. Or in the specified area, the design time series cushion greater frequency run higher. This fully embodies the goals of both size and speed balanced thinking. On the size and speed requirements should not be simply interpreted as raising the level and design engineers perfect sexual pursuit, and should recognize that they are products and the quality and cost of direct relevance. If time series cushion larger design, running relatively high frequency, that the design Jianzhuangxing stronger, more quality assurance system as a whole。 Structured way using examples of words to describe modular doors and modelling. * Verilog HDL has two types of data : data types and sequence data line work types. Line work types that the physical links between ponents and sequence types that abstract data storage ponents. * To describe the level design, the structure can be used to describe any level module example * Design size can be arbitrary。 For example, describing events in the standard sequence of events is not defined. In troduction of DSP Today, DSP is w idely used in the modern techno logy and it has been the key part of many p roducts and p layed more and mo re impo rtant ro le in our daily ly, Northw estern Po lytechnica lUniversity Aviation Microelect ronic Center has p leted the design of digital signal signal p rocesso r co re NDSP25, w h ich is aim ing at TM S320C25 digital signal p rocesso r of Texas Inst rument TM S320 series. By using top 2dow n design flow , NDSP25 is pat ible w ith inst ruct ion and interface t im ing of TM S320C25. Digital signal processors (DSP) is a fit for realtime digital signal processing for highspeed dedicated processors, the main variety used for realtime digital signal processing to achieve rapid algorithms. In today39。 Conversely, if the design of a time series demanding, less than ordinary methods of design frequency then generally flow through the string and data conversion, parallel reproduction of operational module, designed to take on the whole string and conversion and operate in the export module to chip in the data and string conversion from the macro point of view the whole chip meets the requirements of processing speed, which is equivalent to the area of reproduction rate increase. For example. Assuming that the digital signal processing system is 350Mb/s input data flow rate, and in FPGA design, data processing modules for maximum processing speed of150Mb/s, because the data throughput processing module failed to meet requirements, it is impossible to achieve directly in the FPGA. Such circumstances, they should use areavelocity thinking, at least three processing modules from the first data sets will be imported and converted, and then use these three modules parallel processing of data distribution, then the results and string conversion, we have plete data rate requirements. We look at both ends of the processing modules, data rate is 350Mb/s, and in view of the internal FPGA, each submodule handles the data rate is 150Mb/s, in fact, all the data throughput is dependent on three security modules parallel processing subsidiary pleted, that is used by more chip area achieve highspeed processing through the area of reproduction for processing speed enhancement and achieved design. FPGA is the English abbreviation Field of Programmable Gate Array for the site