【正文】 e buffering some temporary data, such as transmit data, waiting data. Data storage district supervise some fixed data memory, such as router data, local host, local address and some renewed data for poweroff protective. F. High Frequency Shielding Protecting Moudule In order to prevent electromagic interference from environment, circuit in our designing system is protected with metal enclosure. At the same time, preventing the digital circuit interfere from the radio frequency circuit in the system, we placed the two circuits in different isolated bin, such as figure 3. There is a small hole with diameter less than 1/4 wavelength in the metal box side, which is either easy to pass the line or prevent the electromagic wave from getting in it. Ⅳ .SYSTEM SOFTWARE DESIGN The realization of system performance depends on its effective and reasonable software control. The design of this software is on the basis of the hardware environment to development a wireless work protocol that have functions as data transmission, avoiding conflict, the retransmission when error occurs, and overtime retry, in order to achieve the design goal. The entire work is posed of a host and many scattered terminals, each terminal must have a wireless transceiver node (this system adopts nRF905 singlechip RF transceiver), any nodes of the entire wireless work has a unique identified address which is posed of an unique identified terminal. For convenience’s sake, each terminal wireless transceiver node addresses of the actual system is set by ourselves (4 bytes). In order to improve the reliability of the system, the protocol is designed as stopwait mode. In data link layer, the send process is roughly as follow. Firstly, the data sources send a connection request to the data targets, and it will transfer data after the data sources respond. Then wait for response from data target after each transmission. If the response is correct, another transmission will start. After all the data transmission is done, the data source will send a request to release channel resources, the transmission is finished when the response from the target is received. The receive process is as follow: the data target will receive data after give a response to the source, and will give a effective or uneffective response, until receive a demolition request. Then, save the data and send a response to end the entire process. data values are serially transferred, pumped into a shift register and are then internally available for parallel processing. Here we already see an important point, that must be considered in the philosophy of SPI bus systems: The length of the shift registers is not fixed, but can differ from device to device. Normally the shift registers are 8Bit or integral multiples of it. Of course there also shift registers with an odd 9 number of bits. For example two cascaded 9Bit EEPROMs can store 18Bit data. If a SPI device is not selected, its data output goes into a highimpedance state, so that it does not interfere with the currently activated devices. When cascading several SPI devices, they are treated as one slave and therefore connected to the same chip select [5]. In figure 4 the cascaded devices are evidently looked at as one larger device and receive therefore the same chip select. The data output of the preceding device is tied to the data Ⅴ .SYSTEM TESTING Because munication between any two nodes may be tested through point to point, in this system Testing Process, munication model