【正文】 ry data to be transmitted at a faster rate per phase change than is possible with BPSK modulation. In fourphase modulation (quadrature PSK or QPSK), the possible phase angles are 0, +90, –90, and 180 degrees。 the largest spur, at the secondharmonic frequency, is about 50 dB below the signal (SFDR = 50 dB).Analog Dialogue 3808, August (2020) 5Do you have tools that make it easier to program and predict the performance of the DDS?The online interactive design tool is an assistant for selecting tuning words, given a reference clock and desired output frequencies and/or phases. The required frequency is chosen, and idealized output harmonics are shown after an external reconstruction filter has been applied. An example is shown in Figure 11. Tabular data is also provided for the major images and harmonics. Figure 11. Screen presentation provided by an interactive design tool. A sinx/x presentation of a typical device output.How will these tools help me program the DDS?All that’s needed is the required frequency output and the system’s reference clock frequency. The design tool will output the full programming sequence required to program the part. In the example in Figure 12, the MCLK is set to 25 MHz and the desired output frequency is set to 10 MHz. Once the update button is pressed, the full programming sequence to program the part is contained in the Init Sequence register. dB0–10–20–30–40–50–60–70–80–90–1600 25MRWB 1K ST200 SECVWB 300FREQUENCY (Hz)dB0–10–20–30–40–50–60–70–80–90–1600 25MRWB 1K ST200 SECVWB 300FREQUENCY (Hz)(a) (b)Figure 10. Output of an AD9834 with a 50MHz master clock and (a) fOUT = MHz (., MCLK/3)。 it effectively sets how many points to skip around the phase wheel. The larger the jump size, the faster the phase accumulator overflows and pletes its equivalent of a sinewave cycle. The number of discrete phase points contained in the wheel is determined by the resolution of the phase accumulator (n), which determines the tuning resolution of the DDS. For an n = 28bit phase accumulator, an M value of 0000...0001 would result in the phase accumulator overflowing after 228 referenceclock cycles (increments). If the M value is changed to 0111...1111, the phase accumulator will overflow after only 2 referenceclock cycles (the minimum required by Nyquist). This relationship is found in the basic tuning equation for DDS architecture: fM fOUTCn=2where: fOUT = output frequency of the DDS M = binary tuning word fC = internal reference clock frequency (system clock) n = length of the phase accumulator, in bitsChanges to the value of M result in immediate and phasecontinuous changes in the output frequency. No loop settling time is incurred as in the case of a phaselocked loop.As the output frequency is increased, the number of samples per cycle decreases. Since sampling theory dictates that at least two samples per cycle are required to reconstruct the output waveform, the maximum fundamental output frequency of a DDS is fC/2. However, for practical applications, the output frequency is limited to somewhat less than that, improving the quality of the reconstructed waveform and permitting filtering on the output. When generating a constant frequency, the output of the phase accumulator increases linearly, so the analog waveform it generates is inherently a ramp.Then how is that linear output translated into a sine wave?A phasetoamplitude lookup table is used to convert the phaseaccumulator’s instantaneous output value (28 bits for AD9833)—with unneeded lesssignificant bits eliminated by truncation—into the sinewave amplitude information that is presented to the (10bit) D/A converter. The DDS architecture exploits the symmetrical nature of a sine wave and utilizes mapping logic to synthesize a plete sine wave from onequartercycle of data from the phase accumulator. The phaseto amplitude lookup table generates the remaining data by reading forward then back through the lookup table. This is shown pictorially in Figure 5. DDS CIRCUITRYREFCLOCKNTUNING WORDSPECIFIES OUTPUTFREQUENCY AS AFRACTION OF REFCLOCK FREQUENCYIN DIGITALDOMAINSIN (x)/xPHASEACCUMULATORAMPLITUDE/SINECONV. ALGORITHMD/ACONVERTERFigure 5. Signal flow through the DDS architecture.What are popular uses for DDS? Applications currently using DDSbased waveform generation fall into two principal categories: Designers of munications