【正文】 and PDFformatted documents. But in order to create, ray, schematic symbols and footprints fur printed circuit boards, information from PDF documents must often be reentereda costly and timeconsuming process when time to infarct is a concern. 39。 由于已長期研究電子設(shè)計(jì)自動化，對于這方面的關(guān)注經(jīng)常受到一些新建的公司抨擊。 從工業(yè)角度上看我們相信是時候推出一種新的設(shè)計(jì)語言處理硬件和軟件的問題，使系統(tǒng)從最初的設(shè)計(jì)規(guī)格直達(dá)最后的檢驗(yàn)。沒有一種現(xiàn)存的方法滿足這些需求，于是davidmann 和 flake 決定發(fā)明一種新的協(xié)同設(shè)計(jì)語言，并命名為superlog。公司已經(jīng)開始和不同標(biāo)準(zhǔn)的組織合作工作達(dá)到其推廣的目的。他們也希望他們的平臺能成為實(shí)際的標(biāo)準(zhǔn)。例如，位向量 0 和 1 的字符串，和所有的在其上將實(shí)行的操作。每一種可使用的工具都有其缺點(diǎn)和優(yōu)勢。 據(jù) Gallagher 說仿真系統(tǒng)之所以運(yùn)行緩慢是由于要使設(shè)計(jì)按部就班的運(yùn)行需要通過許多現(xiàn)場可編程門陣列和許多板?！比欢?，它卻真的是系統(tǒng)的藍(lán)本，高速運(yùn)行可能使目標(biāo) 更真實(shí)。模擬是在一種設(shè)計(jì)和檢驗(yàn)的軟件模型上應(yīng)用向量，查看輸出是否有正確的值。這是一個 verilog模 擬裝置除了沒有通過邏輯發(fā)送 1 和 0，這種工具傳送符號或帶有二進(jìn)制數(shù)值的符號。這樣從一個 32 位降至 16 位的乘數(shù)。首先，連接體的電容，電阻和感應(yīng)系數(shù)不能被忽視。（多數(shù)放置和運(yùn)行工具按順序分析每一種系統(tǒng)規(guī)定參數(shù)的流程圖。該公司是一個虛擬企業(yè)，總部設(shè)在馬薩諸塞州的萬寶路。 的產(chǎn)品是基于 ECIX 標(biāo)準(zhǔn)和 XML 的。這個網(wǎng)站包含一個建立在 AltaVista 技術(shù)上的搜索引擎，可以搜索與設(shè)計(jì)自動化相 關(guān)的各公司網(wǎng)址。因此據(jù) transim 公司首席執(zhí)行官兼總裁解釋說，設(shè)計(jì)者門能夠看到實(shí)際的波狀圖而非字斟句酌的研究數(shù)據(jù)表和一大堆的數(shù)值。 。仿真器則是公司的能源供應(yīng)模擬裝置。市場營銷部副部長 John ott 告訴 spectrum 報說該產(chǎn)品基于華盛頓 Redmond 的微軟公司開發(fā)的操作系統(tǒng)和瀏覽器。但是為了創(chuàng)造圖表式的符號和覆蓋區(qū)為覆蓋電路板， PDF 文件中的信息必須頻繁重新輸入，這是一項(xiàng)耗資巨大且非常浪費(fèi)時間的過程，而且時間對于市場來說非常重要。 網(wǎng)絡(luò)上的電子設(shè)計(jì)自動化 當(dāng)已經(jīng)成立的電子設(shè)計(jì)自動化公司正在努力解決如何在生產(chǎn)線中利用網(wǎng)絡(luò)這個問題時，一些更小更靈敏的公司和一些剛剛起步的公司則致力于創(chuàng)新產(chǎn)品和服務(wù)上，主要在設(shè)計(jì)管理領(lǐng)域創(chuàng)新。第一個包含這項(xiàng)技術(shù)的產(chǎn)品是去年四月生產(chǎn)的 Dolphin。當(dāng)門被放置到芯片上時，連接體在它們之間運(yùn)行?！袄缫粋€模擬檢驗(yàn)器將不停的旋轉(zhuǎn)運(yùn)行但從不產(chǎn)生一個結(jié)果?！? 為了補(bǔ)救， innologic 公司開發(fā)了一種象征性的模擬工具。我們運(yùn)用我們合成的算法，使分開的功能相互融合并且將時間分析貫穿于其中。 Gallagher 解釋說“公司的產(chǎn)品被稱為 certify，它并非以與可重構(gòu)的仿真系統(tǒng)競爭為最初目的。加利福尼亞州Sunnyvale 的市場部經(jīng)理 John Gallagher 說“每秒鐘大約運(yùn)行一百萬圈，設(shè)計(jì)者們不能從他們的仿真系統(tǒng)中有足夠的操作去檢驗(yàn)或理解一些東西，這些東西將靠新一代視頻技術(shù)或?qū)掝l帶的通信技術(shù)運(yùn)行。最不利的結(jié)果將是像 verilog 和 VHDL 之間那樣的僵局，兩者都很盛行，導(dǎo)致電子設(shè)計(jì)自動化的商販們支持兩種技術(shù)而浪費(fèi)雙重的精力。 通過確定新的 C++類庫和模擬型芯， system C 的開發(fā)者已解決了上述問題 ，使得 C++擁有了所有的所需的描述硬件的功能。許多像 synopsys 公司， coware 公司，lucent 技術(shù)公司和德州器具公司等大型權(quán)威的公司已經(jīng)在開放性system C 下聯(lián)結(jié)在一起，開始創(chuàng)立他們下一代設(shè)計(jì)平臺的版本。為了處理已經(jīng)存在的硬 件描述或編程語言的遺留問題， superlog允許 verilog語言和 C 語言模塊輸入并允許其直接使用。第二應(yīng)該使設(shè)計(jì)更為高效。而另外一部分功能將在軟件被描述在編程語言 C 或 C++中結(jié)束。另外，不僅僅是閘門數(shù)量問題，集成芯片的頻率也在加大。for。s correctness is fast being more arduous than doing the design itself. And finally, not only gate counts but chip frequencies also are climbing, so that getting a design to meet its timing requirements without too many design iterations is a receding goal. As is the wont of the electronic design automation (EDA) munity, these concerns are being attacked by startup panies led by a few individuals with big ideas and a little seed money. PARLEZVOUS SUPERLOG? A system on a chip prises both circuitry and the software that runs on it. Such a device may contain an embedded processor core running a software modem. Most often, after the chip39。 FPGA PROCESS DESCRIPTION Three obstacles in particular bedevil ic designers in this dawn of the system on a chip. The first is actually a shortfallthe hardware and software ponents of the design lack a unifying language. Then, as the number of logic gates per chip passes the million marks, verification of a design39。 now closer together, must also be controlled. Several iterations through synthesis and placement may be necessary to achieve the required timing, if it can be acplished at all. The solution proposed by Monterey Design Systems Inc., Sunnyvale, Calif., is called global design technology. This proprietary puting approach simultaneously explores, analyzes, and optimizes all aspects of the physical design. The tint product containing the technology is Dolphin, which was announced in April of last year. Dolphin simultaneously places and router each gate and flipflop using the results or the analysis and maintaining all specified constraints. (Most place androute tools sequentially analyze the layout for each type of constraint.) It performs timing and logic optimization for every placement move. Timing closure is top priority for developers of the Blast Fusion physical design system from Magma Design Automations., Cupertino, Calif. Its methodology, called FixedTiming, brings timing within specified limits without iterating between synthesis and physical design .Basically, he approach fixes timing first, then adjusts cell sizes to achieve the timing requirements. Varying the cell sizes always he tool to supply the right drive strength or the load. EDA ON THE WEB As established electronic design automation panies try to sort out how to utilize the inter in their product Inks, smaller, more agile panies and startups arc coining up with innovative products and services, mainly in the areas or design management. A pioneer in this area i