【正文】 RISC 的數(shù)字信號處理器，但是，確實是取得成果的應(yīng)用結(jié)合起來“的RISC 任務(wù)”和“ DSP 的任 務(wù)。此外，還必須注意，編譯器有但收效甚微復雜的 16 位 DSP 指令集。 16 位 DSP 耗盡形式的“積累”以外的乘法累加器算術(shù)運算是在的 TI DSP產(chǎn)品線：由 90 年代中期，德州儀器的架構(gòu)已增加到 130 多個指示。 C1x ， 39。來源的不確定性，共同在臺式機處理器，可能是災難性的 DSP 的編程。拉伸的 MPEG 2 從 NTSC 系統(tǒng)（國家電視系統(tǒng)承諾， 開球）決議高清不僅需要 6 倍的處理能力，但在新的藍色激光的 DVD 技術(shù)的快速讀取數(shù)據(jù)的磁盤。 3 . 在更高的數(shù)據(jù)速率，算法類似復雜可以編程。工作同時進行，以實現(xiàn) 10 倍性能優(yōu)勢 nonprogrammable 邏輯。做 DSP 的需要可編程？ 編號：這是完全可行的處理數(shù)字信 號不可編程架構(gòu)。相反，實時應(yīng)用不必快速例如，一所醫(yī)院房間心臟監(jiān)視器不需要快 速（ 30 赫茲樣本率），但并不需要實時 。那個技術(shù)和應(yīng)用的數(shù)字信號處理法，相對于模擬信號處理，是很好建立和更為重要的商業(yè)比。據(jù)總裁 Will Strauss 先生和首席分析師 Forward Concepts 公司在“數(shù)字信號處理器出貨量增長了健康百分之二十四在 2021 年，我們預測略高增長的 2021 年，在 25 百分之。在我們周圍汽車 、 數(shù)碼相機 、 MP3 和 DVD 播放器 、 調(diào)制解調(diào)器等等 都應(yīng)用了 DSP。PD7720 were announced at ,achieved 5MHz clock speed ， executing multiplyaccumulates per second at four clock cycles each—enough to allow TouchTone receiver filters to execute in once formidable performance demands of the TouchTone receiver are now ludicrously easy, but new applications in turn arose throughout the last 20 years to put new demands on DSP technology (see figure 1).According to Will Strauss,president and principal analyst at Forward Concepts, “DSP shipments were up a healthy 24 percent in 2021, and we are forecasting a bit higher growth for 2021, at 25 percent. Longer term,we forecast a percent pound growth rate through 2021.”So the game has been: Boost DSP performance, run the algorithm atan acceptable cost, and open up a new mercial is perhaps too glib to project this trend indefinitely into the future,In fact, savvy analysts have periodically predicted the demise of the performance requirements outstripthe ability of programmable DSP architectures to keep up, thus demanding a new approach?or if DSPs are to maintain their historical growth curve， what kinds of tools and architectures are needed? Ultimately， these questions will be answered by creative architects， market petition， and application demands. The goal of this article is to illuminate current and future trends by reviewing how technology and application pressures have shaped DSP architecture in the past. WHAT IS A DSP？ At the outset， it is important to distinguish between digital signal processing and digital signal processors. The techniques and applications of digital signal processing, as pared with analog signal processing，are well established and are more important mercially than ever. Throughout this article,DSP refers to the VLSI (very largescale integration) processor ponent. Therefore， what special demands in digital signal processing make a DSP different from another programmable processor ？ In other words,what makes a DSP a DSP?The Realtime Requirement. The essential application characteristic driving DSP architecture is the requirement to process realtime means that the signal represents physical or “real” events. DSPs are designed to process realtime signals and must therefore be able to process the samples at the rate they are generated and arrive. Adding significant delay,or latency,to the output can be objectionable. While high realtime rates often demand that DSPs be “fast” ,fast and realtime are different example， simulations of VLSI designs must be fast—the faster the better but the application doesn’t fail if the simulator pletes a little slower. Conversely， a realtime application need not be fast—for example,a hospital room heart monitor doesn’t need to be fast (30Hz sample rate) but does need to be realtime。costly powerhungry DSPs today bee the jelly beans of tomorrow. The past 25 years has seen the ascendancy of the userprogrammable DSP as the dominant architectural approach to implementing digital signal processing architecture is driven by a number of specialized application characteristics. Let’s look at a few of these before returning to the architectureal influence of the allimportant realtime constrain. The DSP program must sustain processing at the realtime rate under all fact， the programmer must somehow know that this has been acplished so that the application doesn’t fail in the field. In other words the DSP program must deterministically allocate realtime. Sources of indeterminacy， mon in desktop CPUs， can be catastrophic for the DSP programmer. For faults and cache misses can cause hundreds of cycles to be missed by the CPU as it is idled while the operation is you must sample a value every microsecond, then the page fault or cache miss could cause the window to be a result, DSPs need either fixed memories or caches that can be locked after the program is less critical examples of indeterminacy include branch prediction and datadependent termination of functions such as “divide” . Although nice for the average case, the DSP program must also allow for the worst allocation of realtime not only must be achieved， but traditionally DSPs have made it straightforward to achieve. In newer DSPs, realtime allocation is indeed knowable at pile time, but very careful profiling and iterative programming are often required to achieve the desired oute. ILLUSTRATION: THE TI TMS320C54XXTo bring the discussion down to earth, let’s illustrate with a real DSP. Targeted at the cellphone, TI’s TMS320C54xx was introduced in 1994。 關(guān)鍵詞 DSP；電機控制系統(tǒng) 英特爾 2920 包括芯片（數(shù)字 /模擬）數(shù)字 /模擬和 A / D （模