外文翻譯---三星s3c2442b32位精簡指令應(yīng)用處理器用戶手冊(存儲版)
【正文】 ? 16bit Watchdog Timer ? Interrupt request or system reset at timeout ◆ IICBus Interface 天津工程師范學(xué)院 2020 屆本科生畢業(yè)設(shè)計(jì) 5 ? 1ch MultiMaster IICBus ? Serial, 8bit oriented and bidirectional data transfers can be made at up to 100 Kbit/s in Standard mode or up to 400 Kbit/s in Fast mode. ◆ IISBus Interface ? 1ch IISbus for audio interface with DMAbased operation ? Serial, 8/16bit per channel data transfers ? 128 Bytes (64Byte + 64Byte) FIFO for Tx/Rx ? Supports IIS format and MSBjustified data format ◆ USB Host ? 2port USB Host ? Complies with OHCI Rev. ? Compatible with USB Specification version ◆ USB Device ? 1port USB Device ? 5 Endpoints for USB Device ? Compatible with USB Specification version ◆ SD Host Interface ? Normal, Interrupt and DMA data transfer mode(byte, halfword, word transfer) ? DMA burst4 access support(only word transfer) ? Compatible with SD Memory Card Protocol version ? Compatible with SDIO Card Protocol version ? 64 Bytes FIFO for Tx/Rx ? Compatible with Multimedia Card Protocol version ◆ SPI Interface ? Compatible with 2ch Serial Peripheral Interface Protocol version ? 2x8 bits Shift register for Tx/Rx ? DMAbased or interruptbased operation ◆ Camera Interface ? ITUR BT 601/656 8bit mode support ? DZI (Digital Zoom In) capability ? Programmable polarity of video sync signals ? Max. 4096 x 4096 pixels input support ( 2048 x 2048 pixel input support for scaling) ? Image mirror and rotation (Xaxis mirror, Yaxis mirror, and 180176。 Power Manager ? Onchip MPLL and UPLL: UPLL generates the clock to operate USB Host/Device. MPLL generates the clock to operate MCU at maximum arm and internal, 天津工程師范學(xué)院 2020 屆本科生畢業(yè)設(shè)計(jì) 3 arm and internal,. ? Clock can be fed selectively to each function block by software. — Power mode: Normal, Slow, Idle, Deepstop and Sleep mode — Normal mode: Normal operating mode — Slow mode: Low frequency clock without PLL — Idle mode: The clock for only CPU is stopped. — Stop mode: All clocks are stopped. — DeepStop mode: Arm power off internal clocks are stopped. — Sleep mode: The Core power including all peripherals is shut down. ? Woken up by EINT[15:0] or RTC alarm interrupt from Sleep mode ◆ Stacked Memory ? 256Mbit or 512Mbit mSDR x32, VDD= ? 512Mbit or 1Gbit Nand Flash x8, VDD= ◆ Interrupt controller ? 59 Interrupt sources (One Watch dog timer, 5 timers, 9 UARTs, 24 external interrupts, 4 DMA, 2 RTC, 2 ADC, 1 IIC, 2 SPI, 1 SDI, 2 USB, 1 LCD, 1 Battery Fault, 1 NAND and 2 Camera) ? Level/Edge mode on external interrupt source ? Programmable polarity of edge and level ? Supports Fast Interrupt request (FIQ) for very urgent interrupt request ◆ Timer with Pulse Width Modulation (PWM) ? 4ch 16bit Timer with PWM / 1ch 16bit internal timer with DMAbased or interruptbased operation ? Programmable duty cycle, frequency, and polarity ? Deadzone generation ? Supports e
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鄂ICP備17016276號-1