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外文翻譯---借助dds的精密頻率的一種替代方法-其他專業(yè)(存儲版)

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【正文】 生一個輸出的 正弦波周期 /米,輸出頻率( fDDS)和頻率分辨率( fres)給出由下列公式: m fclk fDDS= 2n fres= fclk/ 2 n 對于 n = 32,有一個 fclk = 33 MHz 的時鐘頻率,頻率分辨率為 兆赫茲。最后階段,這 相對于前一個主要是模擬,包括一個 D / A 轉(zhuǎn)換器在一個過濾器之后。這個術(shù)語 “閉環(huán) ”我們用來記一些反 饋 排序。此外,凡任何參考頻率的脈沖在一個或多個未知一期計算方法也 很常見。 DDS 作為標(biāo)準(zhǔn)信號發(fā)生器在 FC 的投入之 中扮演一定的角色。s output instead of the filtered and hard limited waveform because significant jitter will be encountered. The frequency of the output signal for an nbit system is calculated in the following way。s display are presented. 1 Introduction The most monly used frequency measurement technique adopts counters that count the pulses of the unknown frequency during a predefined time window (aperture). Apart from this, techniques where the pulses of a reference frequency are counted during one or more periods of the unknown one are also mon. In the latter case, the period instead of the frequency is estimated .Some papers in [1] in the literature deal with the problem of low frequency measurement and are focusing in the frequency range of cardiac (heart) signals (a few hertz) or in the mains frequency (5060 Hz). These techniques are actually measuring the period of the signals and use some way to calculate its reciprocal, the frequency. In [2], the frequency is calculated by the method of lookup tables. Others [46] are microprocessor or microcontroller based. The above methods can be characterized as openloop methods . digital counters are used to count during a predefined tinle interval and calculate the result afterwards. Its closedloop form characterizes the proposed method in this paper. By the term closedloop we denote some sort of feedback. A waveform with a known (controlled) frequency is produced within the circuit and is fed back to the frequency parison stage which consecutively forces it to approximate the unknown (input) frequency. The device that produces the above mentioned waveform of controlled frequency is a Direct Digital Synthesizer. 2 Direct Digital Synthesis A typical Direct Digital Synthesizer consists of a RAM containing samples of a sinewave (sine lookup table, LUT). These samples are swept in a controlled manner by the aid of a Frequency Setting Word (FSW), which determines the phase step. A typical FSW is 32bit wide, but 48bit synthesizers leading in higher frequency resolution are also available. A phase accumulator produces the successive addresses of the sine lookup table and generates a digitized sine wave output. The digital part of the DDS, the phase accumulator and the LUT, is called Numerically Controlled Oscillator (NCO). The final stage, which in contrast to the previous one is mostly analog, consists of a D/A converter followed by a filter. The filter smoothes the digitized sinewave, producing a continuous output signal. In the applications where a square wave output is needed, this is obtained by a hard limiter after the filter. It is not equivalent to use . the MSB of the accumulator39。 k ? fin. Description of the prototype hardware For evaluation purposes two prototypes have been built and tested in the laboratory. The first approach was a low frequency instrument (operating up to 15 KHz) . The purpose of this implementation was to study the principles of operation of the proposed method. Next, a higher frequency prototype was built which will be described in more detail here. In order to implement the digital part of the prototype, (Frequency Comparator, Successive Counter, Correction Stage) two PLD devices from Altera (EPF 8064LC6812) were used. These devices are interconnected with the DDS, which is the Q2240I3S1 from Qualm. The DDS has a 32bit input and a 12bit output for the sine lookup table (LUT). The 12bit output of the LUT is fed into the D/A converter, the AD9713B from Analog Devices. Its analog output is connected to an I/V amplifier (currenttovoltage converter). The generated sinewave has upper harmonics, due to the DAC operation. These harmonics are removed from the filters that follow the DAC. The correction stage is implemented partially on the PLDs and partially on the microcontroller. Based on the updown mand of the frequency parator we store the two ex
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