【正文】 nd Uo. Each is measured with respect t~ ground potential. Operational amplifiers are differential devices. By this we mean that the output voltage with respect to ground is given by the expression Uo =A(U+ U) (12Al) where A is the gain of the OpAmp and U+ and U the voltages at inputs. In other words, the output voltage is A times the difference in potential between the two inputs. Integrated circuit technology allows construction of many amplifier circuits on a single posite chip of semiconductor material. One key to the success of an operational amplifier is the cascading of a number of transistor amplifiers to create a very large total gain. That is, the number A in Eq. (12A1) can be on the order of 100,000 or more. (For example, cascading of five transistor amplifiers, each with a gain of 10, would yield this value for A.) A second important factor is that these circuits can be built in such a way that the current flow into each of the inputs is very small. A third important design feature is that the output resistance of the operational amplifier (Ro) is very small. This in turn means that the output of the device acts like an ideal voltage source. We now can analyze the particular amplifier circuit given in Fig. 12A2 using these characteristics. First, we note that the voltage at the positive input, U +, is equal to the source voltage, U + = Us. Various currents are defined in part b of the figure. Applying KVL around the outer loop in Fig. 12A2b and remembering that the output voltage, Uo, is measured with respect to ground, we have I1R1I2R2+U0=0 (12A2) Since the OpAmp is constructed in such a way that no current flows into either the positive or negative input, I =0. KCL at the negative input terminal then yields I1 = I2 Using Eq. (12A2) and setting I1 =I2 =I, U0=(R1+R2)I (12A3) We may use Ohm39。 and 39。N39。 and some transistor outline shapes are found with more than three leads emerging from the base. These, in fact, are integrated circuits (ICs), packaged in the same outline shape as a transistor. More plex ICs are packaged in quite different form, ., flat packages. Power transistors are easily identified by shape~ They are metal cased with an elongated bottom with two mounting holes. There will only be two leads (the emitter and base) and these will normally be marked. The collector is connected internally to the can, and so connection to the collector is via one of the mounting bolts or bottom of the can. A 運(yùn)算放大器 對(duì)應(yīng)于像廣義放大器這樣的電子裝置，存在的一個(gè)問題就是它們的增益 AU或 AI,它們?nèi)Q于雙端口系統(tǒng) (181。這兩個(gè)定律可允許一個(gè)人在沒有詳細(xì)了解運(yùn)算放大器物理特性的情況下設(shè)計(jì)各種電路。兩個(gè)輸入電壓和輸出電壓用符號(hào) U+、 U和 U0 表示。 第二個(gè)重要因素是這些電路是按照流入每一個(gè)輸入的電流都很小這樣的原則來設(shè)計(jì)制作的。如果 A 是一個(gè)非常大的數(shù)，大到足夠使 AR1 (R1 +R2)，那么分式的分母主要由 AR1 項(xiàng)決定，存在于分子和分母的系數(shù) A 就可對(duì)消，增益可用下式表示這表明， AU =(R1+R2)/ R1 (12A5b) 如果 A 非常大，那么電路的增益與 A 的精確值無關(guān)并能夠通 過 R1和 R2的選擇來控制。 B 晶體管 簡(jiǎn)單地說，半導(dǎo)體是這樣一種物質(zhì)，它能夠通過 “ 摻雜 ” 來產(chǎn)生多余的電子，又稱自由電子（ N 型）；或者產(chǎn)生 “ 空穴 ” ，又稱正電荷（ P 型）。其中一個(gè)外部電壓工作方式類似于二極管。實(shí)際上，當(dāng)晶體管下半部為正向偏置時(shí)，底部的 P 區(qū)就像一個(gè)取之不竭的自由電子源（因?yàn)榈撞康?P 區(qū)發(fā)射電子，所以它被稱為發(fā)射極）。換句話說，晶體管的作用相當(dāng)于一個(gè)放大器。（在 PNP 型晶體管中， “ P”代表正）。 在其它 TO 外殼中，三個(gè)引腳可能有類似的三角形形狀（但是基極、集電極和發(fā)射極的位置不一定相同），或三個(gè)引腳排成一條直線。功率晶體管只有兩個(gè)管腳（發(fā)射極和基極），通常會(huì)標(biāo)明。 根據(jù)外殼形狀非常容易識(shí)別功率晶體管。觀看底部時(shí)， “ 三角形 ” 上面的管腳是基極，其右面的管腳（由一個(gè)彩色點(diǎn)標(biāo)出）為集電極，其左面的管腳為發(fā)射極。 因此，基極和集電極相對(duì)于發(fā)射極的極性為負(fù)。但是，在每一種情況下晶體管的工作原理是相同的。如果第二個(gè)電壓被加到晶體管的頂部和底部?jī)蓚€(gè)極之間，并且底部電壓極性相同，那么，流過中間層 N區(qū)的電子將激發(fā)出從晶體管底部到頂部流過的電流。 一個(gè)晶體管有三個(gè)區(qū)域，并從這三個(gè)區(qū)域引出三個(gè)管腳。例，如果運(yùn)算放大器的輸出是 1V，并且 A=100,000, 那么 (U+ = U)=105 V這是一個(gè)非常小、可以忽略的數(shù)，因此可設(shè)U+ = U。對(duì)圖 12A2b