oifspisystempacketinterface-預(yù)覽頁(yè)
【正文】 s t o S y s t e m SPI4 Phase 1: Support up to 10GB/s bidirectional data throughput TXPRTY[3:0] TXSOCP TXEOP TXERR TXVALID RXVALID RXERR RXEOP RXSOCP RXCLK RXDATA[63:0] RXADDR[N1:0] RXSIZE[2:0] RXPRTY[3:0] TX RX RXFULL[3:0] SONET/SDH OC192 10GE WAN/LAN 4xOC48 16xOC12 64xOC3 256xSTS1 First generation。 Ether over SONET (EoS/)。 2 options for status signal rate (full and 1/4 speed) Supports Packet over SONET (POS)。 errorcontrol mode Transmit Link Layer Device Receive Link Layer Device PHY Device Transmit Interface Receive Interface TCTL TDCLK TSTAT TDAT [15:0] RCTL RDCLK RSTAT RDAT [15:0] Data transfer segmented in bursts that are multiples of 16 words (32 bytes) Gb/s minimum data rate per line on data path Gb/s SPI5: System Packet Interface Independent transmit/receive pool status channel Transmit Link Layer Device Receive Link Layer Device PHY Device Transmit Interface Receive Interface TCTL TDCLK TSTAT TDAT [15:0] RCTL RDCLK RSTAT RDAT [15:0] Operates at the same clock rate as the data path Control Word Payload Data Words SPI5: System Packet Interface Anatomy of a Transfer Payload Control Word Address Data Word(s) Address Control Word Optional 32n Bytes (except EndofPacket Transfers
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