oifspisystempacketinterface(更新版)
【正文】 B RXDCK RXDATA [15:0] RXDSC RXS A B S y s t e m t o O p t i c s O p t i c s t o S y s t e m SPI4 Phase 2: TSCLK TSTAT[1:0] RSTAT[1:0] RDCLK RDAT[15:0] RCTL RSCLK TX RX Supports: POS/HDLC EoS/ ATM 10GE LAN 10GE WAN FIFO status out of band。 Ether over SONET (EoS/)。 200 MHz operation implementable in FPGA technology 64 bit interface 200 MHz (lower rate operation supported) HSTL Class 1 signals。 Ether over SONET (EoS/)。 errorcontrol mode Transmit Link Layer Device Receive Link Layer Device PHY Device Transmit Interface Receive Interface TCTL TDCLK TSTAT TDAT [15:0] RCTL RDCLK RSTAT RDAT [15:0] Data transfer segmented in bursts that are multiples of 16 words (32 bytes) Gb/s minimum data rate per line on data path Gb/s SPI5: System Packet Interface Independent transmit/receive pool status channel Transmit Link Layer Device Receive Link Layer Device PHY Device Transmit Interface Receive Interface TCTL TDCLK TSTAT TDAT [15:0] RCTL RDCLK RSTAT RDAT [15:0] Operates at the same clock rate as the data path Control Word Payload Data Words SPI5: System Packet Interface Anatomy of a Transfer Payload Control Word Address Data Word(s) Address Control Word Optional 32n Bytes (except EndofPacket Transfers
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鄂ICP備17016276號-1