【正文】 or input and the other for output, or even a set of registers prising a data storage buffer. ● DMA address register (DAR) － used to store the starting address of the memory buffer area where the block of data is to be read or written. ● Word counter (WC) － the contents specify the number of words in the block of data remaining to be transferred and it is automatically decremented after each word is transferred. ● Control/status register (CSR) － used by the processor to send control information to the DMA controller and to collect the statuses and error information of the DMA controller and the I/O devices attached to it. Using these registers, the DMA controller knows the addresses of the source and destination data blocks, as well as the quantity of data to be transferred. Once the DMA controller acquires the memory bus, the block transfer operation can be performed autonomously using the information contained in these registers, without the continuous involvement of the processor. Besides the abovelisted registers, the DMA controller should contain the control logic of a bus request facility, which performs bus arbitration using the signals of DMA request (DMAR) and DMA acknowledge (DMAA). Bus arbitration is the process of resolving the contention among multiple concurrently operating DMA controllers for acquisition of the memory bus. The selection of the bus master is usually based on the priorities of various DMD devices. Among different DMA devices, the priority order are arranged by the degree urgency of the devices receiving the DMA service, ., according to their speed requirements. There are two approaches to bus arbitration for DMA devices － centralized and distributed － which are similar to the approaches used to identify interrupt sources using signals for interrupt request (INTR) and interrupt acknowledge (INTA). Although the transfer of the data block is performed by the DMA without involvement of the processor, the overall operation of the DMA controller is still determined by the CPU via interrupts. It serves two purposes as follows: (1) Before the DMA controller starts the data transfer, all the registers must be initialized by the processor. (2) When the DMA finishes a block transfer operation, it should inform the processor of pletion by issuing an interrupt, which allows the processor to postprocess the data in the memory buffer area or handle possible error conditions. Therefore, the DMA controller often issued interrupt request (INTR) and receives interrupt acknowledge (INTA) signals. DNA relieves the processor form the burden of I/O function, except for the initialization of the transfer of parameters and the postprocessing of data. It is very efficient when serving highspeed I/O devices. However, the role of DMA is not limited to the area of input/output. In contemporary puter systems, DMA has been developed into a general technique of timesharing the main memory bandwidth between I/O subsystem processing and CPU processing. In the I/O subsystem, highspeed I/O devices, such as disks, CDROMs, DVDs, graphics, video equipment, and highspeed works, want to share main memory bandwidth through the DMA. In the area of central processing and the main memory system, (1) running programs, (2) the operating system, and (3) dynamic RAM refreshing are all sharing the main memory bandwidth, DMA is the appropriate way to implement this timesharing. Faster 16bit Ultra DMA has now replaced the outdated 8bit facilities. Commercially available DMA controller chips now offer multiple channels, allowing concurrent data transfer. For example, one channel can be reserved for DRAM refreshing。學(xué)習(xí)中斷 處理也有助于了解異常事件處理這一普遍性概念，其重要性不但有關(guān) I/O，而且有關(guān)計(jì)算機(jī)與其他系統(tǒng)控制函數(shù)的接口。每個(gè)輸入／輸出端口包含一個(gè)小的寄存器組 , 如數(shù)據(jù)緩沖寄存器 (輸入緩沖器和 /或輸出緩沖器 )、狀態(tài)寄存器和控制寄存器。輸入／輸出寄存器共享主存儲(chǔ)器的同一個(gè)地址空間 , 但是被 映射到一個(gè)特定的專為輸入／輸出預(yù)留的存儲(chǔ)器區(qū)段。任何的一條可以指定存儲(chǔ)器地址的指令都可以執(zhí)行輸入／輸出操作。每個(gè)輸入／輸出寄存器有一個(gè)獨(dú)立的地址空間。它們被稱作端口號(hào)。它有 64 GB 存儲(chǔ)地址空間 (32 位住址 )，同時(shí)，還有一個(gè) 64 KB 輸入／輸出地址空間 (16 位輸入／輸出住址 / 端口號(hào) )。這樣簡(jiǎn)化了輸入／輸出端口和處理器之間的連接，因而導(dǎo)致廉價(jià)的硬件設(shè)計(jì)和實(shí)現(xiàn)。這是因?yàn)橥ǔ］斎耄敵隹偩€周期比較等 價(jià)的存儲(chǔ)器總線周期要長(zhǎng)一些，需要循環(huán)，而這意味著需要設(shè)計(jì)不同的 時(shí)序控制邏輯。對(duì)于直接 輸入／輸出尋址，輸入／輸出不用和主存儲(chǔ)器共享存儲(chǔ)空間，可以維持 一個(gè)單獨(dú)的連續(xù)存儲(chǔ)空間給程序員使用。 如果狀態(tài)顯示 已備好 ，則程序?qū)?zhí)行一條數(shù)據(jù)傳輸指令以完成該輸入／輸出操作；否則，輸入／輸出裝置的忙碌狀態(tài)將會(huì)強(qiáng)迫程序在一個(gè)忙碌等待回路中循環(huán)，直到狀態(tài)變成“已備好”為止。在這一時(shí)間間隔內(nèi)，處理器不能夠運(yùn)行任何的有用計(jì)算 , 而僅服務(wù)于單獨(dú)一個(gè)輸入／輸出裝置。雖然專注式巡查十分低 效 , 但是有時(shí)它是必需的，甚至是不可避免的。在這樣的環(huán)境之下，只有專注式巡查回路才足夠應(yīng)付。這些設(shè)備量測(cè)、收集或記錄數(shù)據(jù) ,通常是按照有規(guī)則的時(shí)間表進(jìn)行周期性的巡查，其規(guī)劃由應(yīng)用對(duì)象的需要決定。 中斷驅(qū)動(dòng)輸入／輸出 中斷驅(qū)動(dòng)輸入 /輸出是一種能避免程控輸入 / 輸出特有的低效忙碌等待回路的方法。 為了響應(yīng)中斷請(qǐng)求 , 處理器將會(huì)首先為正在運(yùn)行中的程序保存好程序計(jì)數(shù)器和狀態(tài)計(jì)數(shù)器的內(nèi)容，然后轉(zhuǎn)移控制到對(duì)應(yīng)的中斷服務(wù)程序，以執(zhí)行要求的輸入 /輸出操作。只有當(dāng)所有的中斷請(qǐng)求都已得到服務(wù)， CPU 才返回被中斷的用戶程序。這一普遍性問(wèn)題稱為異常事件處理。 只有當(dāng)所有 等待著的中斷請(qǐng)求都已經(jīng)得到服務(wù)，才會(huì)喚回被中斷的用戶程序。 在真實(shí)的環(huán)境中，中斷驅(qū)動(dòng)輸入／輸出的過(guò)程比這個(gè)簡(jiǎn)化過(guò)程更為復(fù)雜。 直接存儲(chǔ)器訪問(wèn) 雖然中斷驅(qū)動(dòng)輸入／輸出比被程控輸入／輸出有效率 , 但是它仍然受限于較高的與中斷處理有關(guān)的開(kāi)銷。整個(gè)過(guò)程由 DMA控制器的硬件實(shí)現(xiàn) , 它代替處理器而直接與主存儲(chǔ)器通信。 . DMA控制器能在兩個(gè)不同的模式下工作。在任何一個(gè)時(shí)間段，處理器或 DMA控制器都不能連續(xù)的使用所有的存儲(chǔ)器總線周期。另一方面，對(duì)于更高的輸入／輸出傳輸率，直接內(nèi)存存取操作需要總線時(shí)間能安排在成塊的周期內(nèi)，這稱為爆發(fā)。為這一操作模式設(shè)計(jì)的直接內(nèi)存存取控制器通常結(jié)合一個(gè)數(shù)據(jù)存儲(chǔ)緩沖器，其容量至少與一個(gè) 字塊相匹配。 ● 字計(jì)數(shù)器 (WC) —— 由它的內(nèi)容指定字塊中余下尚待傳輸?shù)淖謹(jǐn)?shù)，每 一個(gè)字傳輸以后字?jǐn)?shù)自動(dòng)減值。 在 上列寄存器之外，直接內(nèi)存存取控制器還應(yīng)該包含總線請(qǐng)求設(shè)備的控制邏 輯 , 它利用直接內(nèi)存存取請(qǐng)求 (DMAR) 和直接內(nèi)存存取回答 (DMAA)信號(hào)執(zhí)行總線仲裁。為直接內(nèi)存存取裝置進(jìn)行總線仲裁有兩個(gè)方法 —— 集中式和分布式，它們和利用中斷請(qǐng)求 (INTR) 和中斷應(yīng)答 (INTA)信號(hào)以辨認(rèn)中斷源的方法是相似的。 DMA 減輕處理器在輸入／輸出功能上的負(fù)擔(dān) ,但叁數(shù)傳輸初始化和數(shù)據(jù)的后處理除外。在輸入／輸出子系統(tǒng)中，高速的輸入／輸出裝置 ，像磁盤(pán)， CDROM， DVD，圖像，視頻設(shè)備和高速網(wǎng)絡(luò)都要經(jīng)過(guò)直接內(nèi)存存取分享主主存儲(chǔ)器的帶寬?，F(xiàn)在可用的商售直接內(nèi)存存取控制器芯片及已經(jīng)提供多個(gè)通道 ,允許并發(fā)的數(shù)據(jù)傳輸。它們被指定專門(mén)的工作，例如浮點(diǎn)運(yùn)算、圖像處理、網(wǎng)絡(luò)通信、大規(guī)模數(shù)據(jù)庫(kù)管