一位全加器電路版圖設(shè)計說明-全文預(yù)覽
【正文】 \13\tanner\bantu\* Cell: Cell0 Version * Extract Definition File: ..\LEdit90\Samples\SPR\example1\* Extract Date and Time: 07/02/2013 22:10.include F:\13\tanner\TSpice70\models\vvdd VDD GND 5va A GND PULSE (0 5 0 5n 5n 50n 100n)vb B GND PULSE (0 5 0 5n 5n 60n 120n)vc C GND PULSE (0 5 0 5n 5n 70n 140n).tran/op 10n 400n method=bdf.print tran v(A) v(B) v(C) v(SUM) v(CO)* Warning: Layers with Unassigned AREA Capacitance.* Poly Resistor ID* Poly2 Resistor ID* N Diff Resistor ID* P Diff Resistor ID* P Base Resistor ID* N Well Resistor ID* Warning: Layers with Unassigned FRINGE Capacitance.* Pad Comment* Poly1Poly2 Capacitor ID* Poly Resistor ID* Poly2 Resistor ID* N Diff Resistor ID* P Diff Resistor ID* P Base Resistor ID* N Well Resistor ID* Warning: Layers with Zero Resistance.* Pad Comment* Poly1Poly2 Capacitor ID* NMOS Capacitor ID* PMOS Capacitor ID* NODE NAME ALIASES* 1 = SUM (29,)* 7 = CO (,)* 12 = B (,99)* 15 = GND (,)* 16 = A (,99)* 17 = C (,99)* 19 = VDD (,)M1 SUM 2 VDD VDD PMOS L=2u W=11u * M1 DRAIN GATE SOURCE BULK (3 71 5 82) M2 2 13 10 VDD PMOS L=2u W=11u * M2 DRAIN GATE SOURCE BULK (26 71 24 82) M3 5 B 6 VDD PMOS L=2u W=11u * M3 DRAIN GATE SOURCE BULK (11 71 9 82) M4 VDD C 5 VDD PMOS L=2u W=11u * M4 DRAIN GATE SOURCE BULK (5 71 3 82) M5 10 C VDD VDD PMOS L=2u W=11u * M5 DRAIN GATE SOURCE BULK (34 71 32 82) M6 6 A 2 VDD PMOS L=2u W=11u * M6 DRAIN GATE SOURCE BULK (17 71 15 82) M7 SUM 2 GND GND NMOS L=2u W=6u * M7 DRAIN GATE SOURCE BULK (3 40 5 46) M8 2 13 8 GND NMOS L=2u W=6u * M8 DRAIN GATE SOURCE BULK (26 40 24 46) M9 3 B 4 GND NMOS L=2u W=6u * M
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