基于嵌入式的數(shù)字鬧鐘設(shè)計(jì)-全文預(yù)覽
【正文】 述語言 HDL 的進(jìn)步。 CPLD/PGFA 幾乎能完成任何數(shù)字器件的功能，上至高性能 CPU，下至簡單的 74 電路。開展 “數(shù)控化 ”工程和 “數(shù)字化 ”工程。為了與臺(tái)灣和美國的設(shè)計(jì)工程師形成更有力的競(jìng)爭，中國的設(shè)計(jì)隊(duì)伍有必要購入一些最新的 EDA 技術(shù)。即使是普通的電子產(chǎn)品的開發(fā)， EDA 技術(shù)常常使一些原來的技術(shù)瓶頸得以輕松突破，從而使產(chǎn)品的開發(fā)周期大為縮短、性能價(jià)格比大幅提高。 EDA。在 Quartus 11 開發(fā)環(huán)境中編譯和仿真了所設(shè)計(jì)的程序，并逐一調(diào)試驗(yàn)證程序的運(yùn)行狀況。 5 1 基于嵌入式的數(shù)字鬧鐘系統(tǒng)設(shè)計(jì) 秦乙 南京信息工程大學(xué) 電子與信息工程 學(xué)院 信息工程 系，南京 210044 摘要 ： 隨著社會(huì)、科技的發(fā)展，人類得知時(shí)間，從觀太陽、擺鐘到現(xiàn)在電子鐘，不斷研究、創(chuàng)新。 1 緒論 ..................................................................... 2 在信息產(chǎn)業(yè)中 EDA產(chǎn)生的影響 .......................................... 2 中國國內(nèi) EDA發(fā)展情況 ................................................ 2 2 FPGA簡介 ................................................................. 2 FPGA概述 ........................................................... 2 FPGA基本結(jié)構(gòu) ....................................................... 3 FPGA編程原理 ....................................................... 3 3 設(shè)計(jì)的總體方案 ........................................................... 4 .............................................................. 4 ............................................................ 4 .................................................... 4 4設(shè)計(jì)的詳細(xì)原理 ............................................................ 5 要模塊 ............................................................ 5 ............................................................ 5 5設(shè)計(jì)的步驟和過程 .......................................................... 6 ............................................................ 6 ............................................................ 7 ........................................................ 8 ........................................................ 9 ..................................... 錯(cuò)誤 !未定義書簽。 摘要和關(guān)鍵詞 ............................................... 錯(cuò)誤 !未定義書簽。 5 參考文獻(xiàn) .................................................. 錯(cuò)誤 !未定義書簽。本文介紹了基于 VHDL 硬件描述語言設(shè)計(jì)的多功能數(shù)字鬧鐘的思路和技巧。 Technology, 210044 ABSTRACT Along with the development of society, science and technology, human beings that time, from view the sun, until now, electric clock pendulum clocks are continuously research and innovation. In order to make the observation time at the same time, can understand other and human closely related information, such as temperature, week, dates, electronic digital clock was born, it sets the time, date, weeks and temperature functions in one, which makes it very convenient, direct display, functional diversity, simple circuit, and many other advantages, conform to the trend of the development of electronic instruments, and has a broad market prospect. EDA technology is dependent on powerful puters in the EDA software platform, with VHDL VHDL for system logic describing means plete design documents, automatically logic optimization and simulation test until realize the set electronic circuit system function. This paper introduces the design based on VHDL VHDL multifunction digital alarm clock of thinking and skills. In Quartus 11 development environments pile and simulation the design process, and then the operation status of debugging validation procedures. The simulation and verification results show that the design method is feasible, and the digital clock can be realized when the alarm clock play music timing adjustment function has certain practical applications. Keywords: the Digital Alarm Clock。電子類的高新技術(shù)項(xiàng)目的開發(fā)也逾益依賴于 EDA 技術(shù)的應(yīng)用。 中國 EDA 市場(chǎng)已漸趨成熟，不過大部分設(shè)計(jì)工程師面向的是 PC 主板和小型
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