【正文】 atchdog timer .equ WTCON, 0x01d30000 Clock Controller .equ PLLCON, 0x01d80000 .equ CLKCON, 0x01d80004 .equ LOCKTIME, 0x01d8000c Memory Controller .equ REFRESH, 0x01c80024 BDMA destination register .equ BDIDES0, 0x1f80008 .equ BDIDES1, 0x1f80028 Predefined constants .equ USERMODE, 0x10 .equ FIQMODE, 0x11 .equ IRQMODE, 0x12 .equ SVCMODE, 0x13 .equ ABORTMODE, 0x17 .equ UNDEFMODE, 0x1b .equ MODEMASK, 0x1f .equ NOINT, 0xc0 .equ IRQ_MODE, 0x40 /* Enable Interrupt Mode (IRQ) */ .equ FIQ_MODE, 0x80 /* Enable Fast Interrupt Mode (FIQ) *//**//* macro define *//**/.macro HANDLER HandleLabel stmdb sp!, {r0r11, ip, lr} /* push r0r11, ip, lr */ ldr r0, =\HandleLabel ldr r1, [r0] mov lr, pc bx r1 /* call interrupt routine */ ldmia sp!, {r0r11, ip, lr} /* pop r0r11, ip, lr */ subs pc, r14, 4 /* interrupt ret */.endm.equ DON, (16).equ DOFF, (06).macro LCD_DOFF OPT ldr r1, =0x01d2001c ldr r2, =0x9aaa str r2, [r1] ldr r2, =0x0 str r2, [r1, 8] GPUPD ldr r2, [r1, 4] bic r2,r2,DON change the GPD6 orr r2,r2,\OPT str r2, [r1, 4] GPDATD.endm.equ LED1, (18).equ LED2, (19).macro LED_ON NUM ldr r1, =0x01d20010 GPCONC ldr r2, =0x0FF5FF55 str r2, [r1] ldr r2, =0x30ff str r2, [r1, 8] GPUPC ldr r2, [r1, 4] bic r2,r2,\NUM str r2, [r1, 4] GPDATC.endm/**//* extern symbol *//**/ .extern Image_RO_Base /* start of rom code */ .extern Image_RO_Limit /* End of ROM code (=start of ROM data) */ .extern Image_RW_Base /* Base of RAM to initialise */ .extern Image_ZI_Base /* Base and limit of area */ .extern Image_ZI_Limit /* to zero initialise */ .extern Main /* The main entry of mon program *//**//* code *//**/ .textENTRY: b ResetHandler /* for debug */ b HandlerUndef /* handlerUndef */ b HandlerSWI /* SWI interrupt handler*/ b HandlerPabort /* handlerPAbort */ b HandlerDabort /* handlerDAbort */ b . /* handlerReserved */ ldr pc, =HandlerIRQ b HandlerFIQ ***IMPORTANT NOTE*** If the H/W vectored interrutp mode is enabled, The above two instructions should be changed like below, to workaround with H/W bug of S3C44B0X interrupt controller. b HandlerIRQ subs pc,lr, 4 b HandlerIRQ subs pc,lr, 4VECTOR_BRANCH: ldr pc, =HandlerEINT0 /*mGA H/W interrupt vector table */ ldr pc, =HandlerEINT1 /* */ ldr pc, =HandlerEINT2 /* */ ldr pc, =HandlerEINT3 /* */ ldr pc, =HandlerEINT4567 /* */ ldr pc, =HandlerTICK /*mGA */ b . b . ldr pc, =HandlerZDMA0 /*mGB */ ldr pc, =HandlerZDMA1 /* */ ldr pc, =HandlerBDMA0 /* */ ldr pc, =HandlerBDMA1 /* */ ldr pc, =HandlerWDT /* */ ldr pc, =HandlerUERR01 /*mGB */ b . b . ldr pc, =HandlerTIMER0 /*mGC */ ldr pc, =HandlerTIMER1 /* */ ldr pc, =HandlerTIMER2 /* */ ldr pc, =HandlerTIMER3 /* */ ldr pc, =HandlerTIMER4 /* */ ldr pc, =HandlerTIMER5 /*mGC */ b . b . ldr pc, =HandlerURXD0 /*mGD */ ldr pc, =HandlerURXD1 /* */ ldr pc, =HandlerIIC /* */ ldr pc, =HandlerSIO /* */ ldr pc, =HandlerUTXD0 /* */ ldr pc, =HandlerUTXD1 /*mGD */ b . b . ldr pc, =HandlerRTC /*mGKA */ b . /* */ b . /* */ b . /* */ b . /* */ b . /*mGKA */ b . b . ldr pc,=HandlerADC