【正文】 過(guò)地址和數(shù)據(jù)線讀回原編寫的數(shù)據(jù)，采用下圖的電路，程序存儲(chǔ)器的地址由P1 和P2 －，數(shù)據(jù)由P0口讀出，、PSEN保持低電平，ALE、EA和RST保持高電平。每個(gè)字節(jié)寫入周期是自身定時(shí)的。3．激活相應(yīng)的控制信號(hào)。編程方法：編程前，須按表6和圖6所示設(shè)置好地址、數(shù)據(jù)及控制信號(hào)。低電壓編程模式適合于用戶在線編程系統(tǒng)，而高電壓編程模式可與通用EPROM編程器兼容。此外，加密位只能通過(guò)整片擦除的方法清除。退出掉電模式的唯一方法是硬件復(fù)位，復(fù)位后將重新定義全部特殊功能寄存器但不改變RAM中的內(nèi)容，在Vcc恢復(fù)到正常工作電平前，復(fù)位應(yīng)無(wú)效，且必須保持一定時(shí)間以使振蕩器重啟動(dòng)并穩(wěn)定工作。需要注意的是，當(dāng)由硬件復(fù)位來(lái)終止空閑工作模式時(shí)，CPU 通常是從激活空閑模式那條指令的下一條指令開(kāi)始繼續(xù)執(zhí)行程序的，要完成內(nèi)部復(fù)位操作，硬件復(fù)位脈沖要保持兩個(gè)機(jī)器周期（24個(gè)時(shí)鐘周期）有效，在這種情況下，內(nèi)部禁止CPU訪問(wèn)片內(nèi)RAM，而允許訪問(wèn)其它端口?？臻e模式可由任何允許的中斷請(qǐng)求或硬件復(fù)位終止。IDL是空閑等待方式，當(dāng)IDL=1，激活空閑工作模式，單片機(jī)進(jìn)入睡眠狀態(tài)。用戶也可以采用外部時(shí)鐘。外接石英晶體（或陶瓷諧振器）及電容CC2接在放大器的反饋回路中構(gòu)成并聯(lián)振蕩電路。XTAL2：振蕩器反相放大器的輸出端。Flash存儲(chǔ)器編程時(shí)，該引腳加上+12V的編程允許電源Vpp，當(dāng)然這必須是該器件是使用12V編程電壓Vpp。EA／VPP：外部訪問(wèn)允許。對(duì)Flash存儲(chǔ)器編程期間，該引腳還用于輸入編程脈沖（PROG）。P3口除了作為一般的I／O口線外，更重要的用途是它的第二功能，如下表所示：P3口還接收一些用于Flash閃速存儲(chǔ)器編程和程序校驗(yàn)的控制信號(hào)。P3口：P3口是一組帶有內(nèi)部上拉電阻的8 位雙向I／O 口。在訪問(wèn)外部程序存儲(chǔ)器或16位地址的外部數(shù)據(jù)存儲(chǔ)器（例如執(zhí)行MOVXDPTR指令）時(shí)，P2口送出高8位地址數(shù)據(jù)。FIash編程和程序校驗(yàn)期間，P1接收低8位地址。P0 口：P0 口是一組8 位漏極開(kāi)路型雙向I／O 口，也即地址／數(shù)據(jù)總線復(fù)用口。掉電方式保存RAM中的內(nèi)容，但振蕩器停止工作并禁止其它所有部件工作直到下一個(gè)硬件復(fù)位。可編程串行UART通道1288字節(jié)內(nèi)部RAM4k字節(jié)可重擦寫Flash閃速存儲(chǔ)器 20%。C to 85176。 10 pF for Ceramic ResonatorsFigure 2. External Clock Drive ConfigurationPowerdown Mode In the powerdown mode, the oscillator is stopped, and the instruction that invokes powerdown is the last instruction executed. The onchip RAM and Special Function Registers retain their values until the powerdown mode is terminated. The only exit from powerdown is a hardware reset. Reset redefines the SFRs but does not change the onchip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock Bits On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the Flash The AT89C51 is normally shipped with the onchip Flash memory array in the erased state (that is, contents = FFH)and ready to be programmed. The programming interface accepts either a highvoltage (12volt) or a lowvoltage (VCC) program enable signal. The lowvoltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the highvoltage programming mode is patible with conventional thirdparty Flash or EPROM AT89C51 is shipped with either the highvoltage or lowvoltage programming mode enabled. The respective topside marking and device signature codes are listed in the following table.The AT89C51 code memory array is programmed bytebybyte in either programming mode. To program any nonblank byte in the onchip Flash Memory, the entire memory must be erased using the Chip Erase Mode. Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3. Activate the correct bination of control signals.4. Raise EA/VPP to 12V for the highvoltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The bytewrite cycle is selftimedand typically takes no more than ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, anattempted read of the last byte written will result in the plement of the written datum on . Once the write cycle has been pleted, true data are valid on all outputs, and