oifspisystempacketinterface-全文預覽
【正文】 ords carry Inband Port Address, start/end of packet indication amp。 Ether over SONET (EoS/)。 ATM over SONET。 200 MHz operation implementable in FPGA technology 64 bit interface 200 MHz (lower rate operation supported) HSTL Class 1 signals。 point to point operation Inband addressing TFCLK TXREFCK TXREFCK RXREFCK Serdes Link Layer NP ATM SAR Framer TMOD[1:0] TDATA [31:0] TENB TXDCK TXDATA [15:0] TXDSC TXCKSRC RXREFCK D C A B TADR[1:0] DTPA[3:0] STPA RSX RXDCK RXDATA [15:0] RXDSC RXS A B S y s t e m t o O p t i c s O p t i c s t o S y s t e m SPI3: OIF 8 bit operation supports 1xOC12 (622 MB/s) TPRTY TSOP TEOP TERR TSX RERR REOP RSOP RVAL PTPA RFCLK RENB RDAT[31:0] RMOD[1:0] RPRTY TX RX Supports: Packet over SONET ATM over SONET Frame Relay over SONET Error indication signal Data transfer independent of line bit rate Transfers ATM cells, packets including IP, FR, etc. Flow control on interface TXCLK TXREFCK TXREFCK RXREFCK Serdes Link Layer NP ATM SAR Framer TXSIZE[2:0] TXDATA [63:0] TXADDR[N1:0] TXDCK TXDATA [15:0] TXDSC TXCKSRC RXREFCK D C A B TXSTART TXFULL[3:0] RXSTART RXDCK RXDATA [15:0] RXDSC RXS A B S y s t e m t o O p t i c s O p t i c
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