【正文】 ith respect to the original image。 memory controller unit, weightupdating unit, and thresholding unit. The modules and their interconnections are illustrated in Figure 2. The “memory controller unit” generates timing for control signals to send/receive image pixels data to/from the memory. The “weightupdating unit” is in fact an arithmetic processor to calculate the weights and threshold values. Each input pixel is read from memory, pared with the weights and the closer weight is updated. The update is done based on the difference between the input pixel and the weight, scaled by a learning rate factor. Once a plete frame of the image is processed, the center of background and foreground clusters is puted. “Thresholding unit” determines the threshold value by averaging the weights. Then every single pixel of the same image is fetched from memory via memory controller unit. Each read pixel is pared to the threshold value, and the result is written back to the memory. Memory ControllerUnitWeight UpdateUnitThresholding UnitReadyDataReadDoneAddressDataReadWriteDoneWeightsDoneStartAddress Figure 2 : Thresholding block diagram. All of these units are modeled with VHDL. In the following section, each unit is described in more details. WeightUpdating Unit The thresholding process starts from the weightupdating unit. This process is controlled by an external signal, start of frame, if this signal is not activated the plete system remains in the reset state. The system starts operating only when this signal is active. Then it activates a control signal to request a read operation for a pixel from the memory controller unit. It also puts the address of the pixel on the address bus. By the time the memory controller unit drives the done signal high, the valid data is ready on the data bus. After the weights are updated for the pixel, another request for a read operation for the next pixel is set. This process continues until the end of frame signal is activated by the memory controller unit. As the result two weight values are output to the thresholding unit. This unit is implemented in VHDL. The weightupdating circuitry is puting the output data based on the input data so it is dominated by its data path rather than control or storage. In fact, the major arithmetic operations on the input data value are provided here. The work is implemented with two weights 1W and 2W . The input image, I, is pared to them and either of weights are updated with equations (4) and (5). )1(*11 oldioldnew WIWW ?+= α (4) )2(*22 oldioldnew WIWW ?+= α (5) Each weight is pared to the input and the parator finds the smaller inputweight distance. Therefore the parator must pare the absolute values. The result of the parator is used to determine the weight with smaller distance to be updated. The difference for each weight is scaled by the learning rate and the result is added to the weight value to obtain the updated value. For each input pixel the parator allows only one weight to get updated while the other remains unchanged. In the weightupdating unit some signed operators are used, such as calculating the differences, so the internal data path has to be signed. However, the basic data type of the VHDL is limited when using the language for RTL design. To do the signed arithmetic with the data in the circuitry design, a strong and supportive VHDL package is required. Two IEEE standard packages numeric_std and std_logic_arith are most mon used packages. We used the numeric_std package for the data path signed arithmetic in the VHDL implementation. This package defines arithmetic over std_logic vectors and integers. The std_ logic_ arith package has less uniform support for mixed integer/signal arithmetic and has a greater tendency for differences between tools. The numeric_std also defines types signed and unsigned, which are std_logic vectors on which the signed or unsigned arithmetic can be performed simply. In this algorithm we need real numbers for some parts of the numerical putation. For example the learning rate is a real number between 0 and 1. There are many ways to represent nonintegers, such as floating point. Floating point allows a wide range of values to be represented。 adjacent regions should have significantly different values。FPGA Implementation of RealTime Adaptive Image Thresholding Elham Ashari Department of Electrical and Computer Engineering, University of Waterloo Richard Hornsey Department of Computer Science amp。 region interiors should be without artifacts。 its numerical stability has been well studied in the research literature. But floatingpoint arithmetic units consume significantly greater hardware resources than the integer arithmetic [20] and this make it more suitable for million gate FPGA like Xilinx Virtex series. Of course so many enhancement and optimization has been proposed for the real numbers [21] [22]. Since the resource of the current FPGA device is limited and because the focus of this algorithm is not on the high precision of the numbers, all numbers are represented in integer and an approximation is applied for the arithmetic. Thresholding Unit Once the weightupdating unit receives the end of frame signal indicating the pletion of one frame weight update process, the weight values are sent to the thresholding unit. First the threshold value is calculated by averaging the weight values. Then the thresholding unit puts the address of the first pixel on the address bus and activates the read control signal. After the memory controller unit drives done signal high, this unit read the pixel from the data bus and pares it to the threshold value. If the read value is less than the threshold the write control signal is driven high and ‘0’ is output to the data