【正文】 ee array allows designers to represent up to ASlC gates. And routing delays are greatly curtailed because each chip is no more than two hops away from any other chip in the array. The pany% product, called Certify, is not intended to pete with reconfigurable emulation systems, which are very effective at debugging designs during the internal design process, explained Gallagher. Rather, it is a true prototype of the system, running at speeds that may approach the real thing. Certify handles three fundamental operations, said Gallagher. The first is partitioning, or breakings up the ASIC register trans fer level (RTL) code into different FPGAs. It does synthesis, turning the RTL code into ASIC gates equivalent to the final ASIC gates. Then it does timing analysis. We haven39。VHDL language。 IC。s functionality is spelled out, usually on paper, the hardware potent is handed off to the circuit designers and the software is given to the pro grammars, to meet up again at some later date. The part of the chips functionality that will end up as logic gates and transistors is writ ten in a hardware design languageVirology or VHDL, while the part that will end up as software is most often described in the programming language C or C++. The use of these disparate languages hampers the ability to describe, model, and debug the circuitry of the IC and the software in a coherent fashion. It is time, many in the industry believe, for a new design language that can cope with both hardware and software from the initial design specification right through to final verification. Just such a new language has been developed by CoDesign Automation Inc., San Jose, Calif. Before launching such an ambitious enterprise, cofounders Simon Davidmann, who is also chief operating officer, and Peter Flake ruled out the usefulness of extending an existing language to meet systemonchip needs. Among the candidates for extension were C, C++, Java, and Verilog. A design language should satisfy three requirements, maintained Davidmann. It should unify the design process. It should make designing more efficient. And it should evolve out of an existing methodology. None of the existing approaches filled the bill. So Davidmann and Flake set about developing new codesign language called Superlog. A natural starting point was a blend of Virology and C since from an algorithm point of view, a lot of Virology is built on C, explained Davidmann. Then they spiced the blend with bits and pieces of VHDL and Java. From Virology and VHDL, Superlog has acquired the ability to describe hardware aspects of the design, such as sequential, binatorial, and multivalued logic. From C and Java it inherits dynamic processes and other software constructs. Even functions like interfaces, protocols, and state machines, which till now have often been done on paper, can be described in the new language. To support legacy code written in a hardware description or programming language, Superlog allows both Virology and C modules to be imported and used directly. It is important for the language to be in the public domain, according to Davidmann. The pany has already begun to work with various standards organizations to this end. Not to be overlooked is the need for a suite of design tools based on the language. Recently CoDesign identified a number of electronic design automation panies, among them Magma Design Automation, Sente, and Viewlogic, that will develop tools based on Superlog. CoDesign will also develop products for the front end of the design process. ARACE TO THE FINISH Not everyone is convinced that a new language is needed. SystemC, a modeling platform that extends the capabilities and advantages of C/C++ into the hardware domain has been proposed as an alternative. Such large and powerful panies as Synopsys, Coware, Lucent Technologies, and Texas Instruments have banded together under the Open SystemC Initiative to promote their version of the nextgeneration design platform. To get SystemC off to a running start, the group offers a modeling platform for download off their Web site free of charge. Their hope is also to make their platform the de facto standard. The rationale for developing SystemC was straightforward, according to Joachim Kunkel, general manager and vice president of the System Level Design Business Unit at Synopsys. It was to have a standard language in which semiconductor vendors,