【正文】
hat are extemally being pulled low will source current (IlL) because of the intemal pullups. 1n addition, and can be configured to be the timer/counter 2 extemal count input() and the timer/counter 2 trigger input (), respectively, as shown in the following table. Port 1 also receives the loworder address bytes during Flash programing and verification. Port 2 Port 2 is an 8bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When Is are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are extemal1y being puIled low will source current (IIL) because ofthe intemal pullups. Port 2 emits the highorder address byte during fetches from extemal program memory and during accesses to extemal data memory that use 16bit addresses (MOVX DPTR). 1n this application, Port 2 uses strong intemal pullups when emitting 1s. During accesses to external data memory that use 8bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 a1s0 receives the highorder address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8bit bidirectional 1/0 port with internal Port 3 output buffers can sink/source four TTL inputs. When Is are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are extemal1y being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various specia1 features of the AT89C51, as shown in the following tab1e. Port 3 also receives some contro1 signa1s for F1ash programming and verification. RST Reset input. A high on this pin for two machine cycles while the osci1lator is running resets the device. ALEIPROG Address Latch Enab1e is an output pu1se for 1atching the 10w byte of the address during accesses to externa1 memory. This pin is a1so the program pu1se