【正文】 據(jù)。 此外， AT89C51 設(shè)有穩(wěn)態(tài)邏輯，可以在低到零頻率的條件下靜態(tài)邏輯，支持兩種軟件可選的掉電模式。 讀片內(nèi)簽名字節(jié)： 讀簽名字節(jié)的過程和單元 030H、 031H 及 032H 的正常校驗相仿，只需將 和 保持低電平，返回值意義如下： (030H)=1EH 聲 明產(chǎn)品由 ATMEL 公司制造 (031H)=51H 聲明為 AT89C51 單片機 (032H)=FFH 聲明為 12V 編程電壓 (032H)=05H 聲明為 5V 編程電壓 編程接口： 采用控制信號的正確組合可對 Flash 閃速存儲陣列中的每一代碼字節(jié)進行寫入和存儲器的整片擦除，寫操作周期是自身定時的，初始化后它將自動定時到操作完成。Compatible with instruction set of MCS51 products Fully static operation: 0 Hz to 24 MHz Two 16bit Timer/Counters Onchip oscillator and clock circuitry GND: Ground Port 3: Port 3 is an 8bit bidirectional I/O port with internal Port 3 output buffers can sink/source four TTL inputs. When the P3 I write 1 after, they are internal pullup is high, and used as input. As input, due to the external pulldown for the low, P3 port output current (ILL) This is due to pullup39。PSEN ： Program Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. Ready/ BUSY : The progress of byte programming can also be monitored by the RDY/ BSY output signal. is pulled low after ALE goes high during programming to indicate BUSY. is pulled high again when programming is done to indicate READY. Oscillator Characteristics： XTAL1 and XTAL2 respectively, reverse amplifier input and output. The reverse amplifier can be configured as onchip oscillator. Shi Jing oscillation and ceramic oscillation can be used. If using an external clock source drive the device, XTAL2 should not take. More than input to the internal clock signal through a twoway flipflop, so the external clock signal pulse width without any request, but must ensure that the highlow pulse width requirements. Clock Oscillator： XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an onchip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide by two flip trigger, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode： In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the onchip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. Onchip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Powerdown Mode: In the powerdown mode, the oscillator is stopped, and the instruction that invokes powerdown is the last instruction executed. The onchip RAM and special function registers retain their values until the powerdown mode is terminated. The only exit from powerdown is a hardware reset. Reset redefines the special function registers but does not change the onchip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. Progra