電子科技大學(xué)實(shí)驗(yàn)報(bào)告格式(文件)
【正文】 ut , j_clr =clr_A , j_en =ena_A , s_en =lock_A)。：entity counter10 isPort(clr : in STD_LOGIC。daout : out STD_LOGIC_VECTOR(3 downto 0))。139。en : in STD_LOGIC。architecture Behavioral of counter6 is signal count:std_logic_vector(2 downto 0)。eng : in STD_LOGIC。daout2 : out STD_LOGIC_VECTOR(3 downto 0)。daout6 : out STD_LOGIC_VECTOR(2 downto 0))。END COMPONENT。co : OUT std_logic。clk : IN std_logic。END COMPONENT。begin Inst_fenpingqi_10: fenpingqi_1k_100 PORT MAP（clk =clk，q = clk_100)。Inst_counter6_1: counter6 PORT MAP（clr =clear ，clk =clk_100，en =co_out3，co =co_out4 ，daout = daout4)。：entity control isPort(clk : in STD_LOGIC。j_en : out STD_LOGIC。signal next_state:std_logic_vector(1 downto 0)。end fenpingqi_48m_1k。and clk39。elsecounterqend Behavioral。architecture Behavioral of fenpingqi_1k_100 is signal counter:STD_LOGIC_vector(3 downto 0)。event)then if counter=9 then countercounter：entity display isPort(clk_1k : in STD_LOGIC。t11 : in STD_LOGIC_VECTOR(2 downto 0)。seg : out STD_LOGIC_VECTOR(7 downto 1))。signal seg7:std_logic_vector(7 downto 1):=“1111110”。 then digbcdbcdbcdbcdbcdbcdbcdbcdbcdseg7seg7seg7seg7seg7seg7seg7seg7seg7seg7seg7outputoutputoutputoutputoutputoutputoutputoutputoutput：entity latch isPort(t_0 : in STD_LOGIC_VECTOR(3 downto 0)。t_2 : in STD_LOGIC_VECTOR(3 downto 0)。t00 : out STD_LOGIC_VECTOR(3 downto 0)。t22 : out STD_LOGIC_VECTOR(2 downto 0))。 then t0：entity keydb isPort(clk : in STD_LOGIC。architecture Behavioral of keydb is signal k1,k2:STD_LOGIC。039。begin process(clk,key_in)begin if clk39。key_out : out STD_LOGIC)。architecture Behavioral of latch isbegin process(display_in,t_0,t_00,t_1,t_11,t_2,t_22)begin if display_in=39。t11 : out STD_LOGIC_VECTOR(2 downto 0)。display_in : in STD_LOGIC。t_1 : in STD_LOGIC_VECTOR(3 downto 0)。event and clk_1k=39。architecture Behavioral of display is signal dig:std_logic_vector(2 downto 0):=“000”。t22 : in STD_LOGIC_VECTOR(2 downto 0)。t00 : in STD_LOGIC_VECTOR(3 downto 0)。139。q : out STD_LOGIC)。039。begin process(clk)begin if(clk=39。begin key if key=“10” then next_state case key is when“10”=next_statenext_statenext_state if key=“01” then next_state case key is when“10”=next_statenext_statenext_state j_clr j_clr j_clr j_clr（2個(gè)）： entity fenpingqi_48m_1k isPort(clk : in STD_LOGIC。end control。p : in STD_LOGIC。Inst_counter6_2: counter6 PORT MAP（clr =clear，clk =clk_100，en =co_out5，co =ou，daout = daout6)。Inst_counter10_2: counter10 PORT MAP（clr = clear，clk =clk_100 ，en = co_out1，co = co_out2，daout = daout2)。signal clr_A,ena_A:std_logic。co : OUT std_logic。END COMPONENT。clk : IN std_logic。architecture Behavioral of counter is COMPONENT fenpingqi_1k_100 PORT（clk : IN std_logic。daout4 : out STD_LOGIC_VECTOR(2 downto 0)。ou : out STD_LOGIC。139。daout : out STD_LOGIC_VECTOR(2 downto 0))。：entity counter6 isPort(clr : in STD_LOGIC。architecture Behavioral of counter10 is signal count:std_logic_vector(3 downto 0)。en : in STD_LOGIC。Inst_display: display PORT MAP(clk_1k = clk_1k, t0 =daoA , t00 =daoB, t1 =daoC, t11 =daoD, t2 =daoE, t22 =daoF, output = Out8, seg =Seg)。Inst_keydb1: keydb PORT MAP（clk =clk_1k ，key_in = S_S，downtokey_out =S_S_out)。signal dao4,dao6,daoD,daoF:std_logic_vector(2 downto 0)。signal S_S_out,S_R_out:std_logic。output: out STD_LOGIC_VECTOR(7 downto 0)。t1 : IN std_logic_vector(3 downto 0)。END COMPONENT。t1 : OUT std_logic_vector(3 downto 0)。t_22 : IN std_logic_vector
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鄂ICP備17016276號-1