【正文】 s opposed to a “regular” mercialofftheshelf (COTS) device or application specific integrated circuit (ASIC) where no hardening has been performed, one needs to determine how validated is the design library as opposed to determining the device hardness. That is, by using test chips, can we “qualify” a future device using the same library? Consider if Vendor A has designed a new HBD library portable to foundries B and C. A test chip is designed, tested, and deemed acceptable. Nine months later a NASA flight project enters the mix by designing a new device using Vendor A’s library. Does this device require plete radiation qualification testing? To answer this, other questions must be plete was the test chip? Was there sufficient statistical coverage of all library elements to validate each cell? If the new NASA design uses a partially or insufficiently characterized portion of the design library, full testing might be required. Of course, if part of the HBD was relying on inherent radiation hardness of a process, some of the tests (like SEL in the earlier example) may be waived. Other considerations include speed of operation and operating voltage. For example, if the test chip was tested statically for SEE at a power supply voltage of , is the data applicable to a 100 MHz operating frequency at ? Dynamic considerations (., nonstatic operation) include the propagated effects of Single Event Transients (SETs). These can be a greater concern at higher point of the considerations is that the design library must be known, the coverage used during testing is known, the test application must be thoroughly understood and the characteristics of the foundry must be known. If all these are applicable or have been validated by the test chip, then no testing may be necessary. A task within NASA’s Electronic Parts and Packaging (NEPP) Program was performed to explore these types of considerations.III. HBD TECHNOLOGY EVALUATION USING THE 8051 MICROCONTROLLERWith their increasing capabilities and lower power consumption, microcontrollers are increasingly being used in NASA and DOD system designs. There are existing NASA and DoD programs that are doing technology development to provide HBD. Microcontrollers are one such vehicle that is being investigated to quantify the radiation hardness improvement. Examples of these programs are the 8051 microcontroller being developed by Mission Research Corporation (MRC) and the IAμE (the focus of this study). As these HBD technologies bee available, validation of the technology, in the natural space radiation environment, for NASA’s use in spaceflight systems is 8051 microcontroller is an industry standard architecture that has broad acceptance, wideranging applications and development tools available. There are numerous mercial vendors that supply this controller or have it integrated into some type of systemonachip structure. Both MRC and IAμE chose this device to demonstrate two distinctly different technologies for hardening. The MRC example of this is to use temporal latches that require specific timing to ensure that single event effects are minimized. The IAμE technology uses ultra low power, and layout and architecture HBD design rules to achieve their results. These are fundamentally different than the approach by AeroflexUnited Technologies Microelectronics Center (UTMC), the mercial vendor of a radiation– hardened 8051, that built their 8051 microcontroller using radiation hardened processes. This broad range of technology within one device structure makes the 8051an ideal vehicle for performing this technology evaluation.The objective of this work is the technology evaluation of the CULPRiT process [3] from IAμE. The process has been baselined against two other processes, the standard 8051 mercial device from Intel and a version using stateoftheart processing from Dallas Semiconductor. By performing this sidebyside parison, the cost benefit, performance, and reliability trade study can be the performance of the technology evaluation, this task developed hardware and software for testing microcontrollers. A thorough process was done to optimize the test process to obtain as plete an evaluation as possible. This included taking advantage of the available hardware and writing software that exercised the microcontroller such that all substructures of the processor were evaluated. This process is also leading to a more plete understanding of how to test plex structures, such as microcontrollers, and how to more efficiently test these structures in the future.IV. TEST HARDWAREThe 8051 Device Under Test (DUT) was tested as a ponent of a functional puter. Aside from DUT itself, the other ponents of the DUT puter were removed from the immediate area of the irradiation beam. A small card (one per DUT package type) with a unique hardwired identifier byte contained the DUT, its crystal, and bypass capacitors (and voltage level shifters for the CULPRiT DUTs). This DUT Board was connected to the Main Board by a short 60conductor ribbon cable. The Main Board had all other ponents required to plete the DUT Computer, including some which nominally are not necessary in some designs (such as external RAM, external ROM and address latch).The DUT Computer and the Test Control Computer were connected via a serial cable and munications were established between the two by the Controller (that runs custom designed serial interface software). This Controller software allowed for manding of the DUT, downloading DUT Code to the DUT, and realtime error collection from the DUT during and post irradiation. A 1 Hz signal source provided an external watchdog timing signal to the DUT, whose watchdog output was monitored via an oscilloscope. The power supply was monitored to provide indicati。本次設(shè)計能夠順利完成，首先，我要感謝我的母校—華北水利水電學(xué)院，是他為我們提供了學(xué)習(xí)知識的土壤，是我們在這里茁壯成長；其次，我要感謝電力學(xué)院的老師們，它們不僅教會我們專業(yè)方面的知識，而且教會我們做人做事的道理；尤其要感謝在本次設(shè)計中給予我大力支持和幫助的張紅濤老師和張恒源老師，在設(shè)計過程中，每有問題，張紅濤老師和張恒