oifspisystempacketinterface(文件)
【正文】 faster and narrower interface 16 bit LVDS interface 800 MHz (622 MHz minimum operation) TDCLK TXREFCK TXREFCK RXREFCK Serdes Link Layer NP ATM SAR Framer TDAT [15:0] TCTL TXDCK TXDATA [15:0] TXDSC TXCKSRC RXREFCK D C A B RXDCK RXDATA [15:0] RXDSC RXS A B S y s t e m t o O p t i c s O p t i c s t o S y s t e m SPI4 Phase 2: TSCLK TSTAT[1:0] RSTAT[1:0] RDCLK RDAT[15:0] RCTL RSCLK TX RX Supports: POS/HDLC EoS/ ATM 10GE LAN 10GE WAN FIFO status out of band。 10GE WAN/LAN PHY (IEEE ) SPI5: System Packet Interface OC768 System Interface for Physical and Link Layer Devices Transmit Link Layer Device Receive Link Layer Device PHY Device Data Transmit Interface Status Data Status Receive Interface System Packet Interface (SPI) SERDES Device SERDES Framer Interface (SFI5) SPI5: System Packet Interface Pointtopoint connection (. single PHY / single Link Layer device) Transmit Link Layer Device Receive Link Layer Device PHY Device Transmit Interface Receive Interface TCTL TDCLK TSTAT TDAT [15:0] RCTL RDCLK RSTAT RDAT [15:0] Support for 256 ports with address extension to 2144 ports Pointtopoint connection Support for 256 ports SPI5: System Packet Interface Control w
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