【正文】 驗證程序等。 二、實驗內容： 1. 根據帶中斷功能的復雜模型機的微程序流圖，畫出狀態(tài)機 描述圖； 2. 分析每個狀態(tài)所需的控制信號，產生控制信號表，并用 VHDL 語言來設計程序，實現狀態(tài)機描述的功能； 3. 用 Quartus 軟件進行編譯鏈接，選擇器件，定義管腳，編程下載，然后用 CM3P 聯(lián)機測試每一條機器指令的功能。 三、 項目要求及分析： 實驗要求設計帶中斷功能的復雜模型機的硬布線控制器，可先參照前面帶中斷處理能力的模型機設計實驗畫出微程序流程圖，參照二進制微代碼表設控制信號表。 狀態(tài)圖： 計算機組成原理實驗報告 2 S 0S 1S 3 3S 3 4 S 3 5 S 3 6 S 3 7 S 3 8S 2S 3S 5 4S 5 5S 5 6S 5 7S 5 8S 5 9S 5 3S 5 2S 5 1S 5 0S 4 9S 4 8S 6 0S 6 1S 4 7S 6 2S 4S 5S 6S 7S 8S 9S 1 0S 1 6S 1 7 S 1 8S 1 9S 2 0S 2 1S 2 2S 2 3S 2 4S 2 5S 2 6S 2 8S 2 9S 3 0S 3 1S 3 2S 3 9S 4 0S 4 1S 4 2S 4 3S 4 4S 4 5S 4 6S 1 2 S 1 3 S 1 4 S 1 5S 1 1S 2 7返 回S 1返 回S 1返 回S 1返 回S 1返 回S 1返 回S 1返 回S 1返 回S 1返 回S 1返 回S 1返 回S 1返 回S 1返 回S 1返 回S 1返 回S 1返 回S 1控制狀態(tài)表： INTA/WR/RD/IOM/S3/S2/S1/S0/LDA/LDB/LDR0/LDSP/L0AD/LDAR/LDIR/ALUB/RSB/RDB/RIB/SPB/PCB/LDPC/STI/CLI S0 100000000000100111111010 S1 100000000000100111111011 S2 100000000000110111110111 S3 101000000000101111111011 S4 100000000100100101111011 S5 100010010010100011111011 S6 100000000100100101111011 S7 100000100010100011111011 S8 101000000000110111111011 S9 101100000010100111111011 S10 101000000000110111111011 S11 100000000000100111111011 S12 101000000010100111111011 S13 110000000000100110111011 S14 100000000000000011111111 計算機組成原理實驗報告 3 S15 100000000000100111111011 S16 110100000000100101111011 S17 101000000010100111111011 S18 110000000000100101111011 S19 100000001000100111101011 S20 100011010001100011111011 S21 100011000001100011111011 S22 100000000000110111101011 S23 101000000010100111111011 S24 100011000001100011111011 S25 100000000000110111101011 S26 101000000000000111111111 S27 100000000000000011111111 S28 101000001000100111111011 S29 101000000000110111111011 S30 101000000000110111111011 S31 101000001000100111111011 S32 101000000000110111111011 S33 000000000000110111101011 S34 110000000000100111110011 S35 100000001000100111101011 S36 100011010001100011111011 S37 000000000000110111111011 S38 101000000000000111111111 S39 101000001000100111111011 S40 100000000100100111011011 S41 100010010000110011111011 S42 100010011000100011111011 S43 101000001000100111111011 S44 100000000100100111110011 S45 100010010000110011111011 S46 100010011000100011111011 S47 100000001000100110111011 S48 100000001000100110111011 S49 100000000000110111110111 S50 100000000000110111110111 S51 100000000010100101111011 S52 100000000000100111111011 S53 100000000000110111110111 S54 100000000000100111111001 S55 100000000000100111111010 S56 100000000000110111101011 S57 100000001000100111101011 S58 100000001000100111101011 S59 100000000000110111110111 計算機組成原理實驗報告 4 S60 100000000000110111110111 S61 100000000000110111110111 S62 100000000000110111110111 控制引腳圖： 五、 調試運行結果： VHDL 程序： LIBRARY IEEE。 INTR : IN STD_LOGIC。 ARCHITECTURE CONTROLLER_ARCH OF CONTROLLER IS TYPE STATE IS (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16, S17,S18,S19,S20,S21,S2