【正文】 T89C51 pins allotment (2) interrupt introduction AT89C51 has six interrupt sources: two external interruption, (and), three timer interrupt (timer 0, 1, 2) and a serial interrupts. Each interrupt source can be passed buy bits or remove IE the relevant special register interrupt allow control bit respectively make effective or invalid interrupt source. IE also includes an interrupt allow total control bit EA, it can be a ban all interrupts. IE. Six is not available. For AT89C51, IE. 5 bits are also not be used. User software should not give these bits write 1. They AT89 series for new product reserved. Timer 2 can be TF2 and the T2CON registers EXF2 or logical triggered. Program into an interrupt service, the sign bit can be improved by hardware qing 0. In fact, the interrupt service routine must determine whether TF2 or EXF2 activation disruption, the sign bit must also by software qing 0. Timer 0 and 1 mark a timer TF0 and TF1 has been presented in the cycle count overflow S5P2 074 bits. Their value until the next cycle was circuit capture down. However, the timer 2 marks a TF2 in count overflow of the cycle of S2P2 074 bits, in the same cycle was circuit capture down (3) external clock driving characteristics symbols parameters minimum The maximum unit 1/TCLCL OscillatorFrequency 0 24 MHz TCLCL Clock Period ns TCHCX High Time 15 ns 14 TCLCX Low Time 15 ns TCLCH Rise Time 20 ns TCHCL Fall Time 20 ns Table 1 (4) leisure and power lost pattern external pins state mode Program memory ALE ^psen Port0 Port1 Port2 Port3 idle internal 1 1 data data data Data Idle External 1 1 float Data data Data Power down Internal 0 0 Data Data Data Data Power down External 0 0 float data Data data Table 2 About 8255 chip features: (1)A parallel input/output LSI chips, efficacy of I/O devices, but as CPU bus and peripheral interface. (2)It has 24 programmable Settings of I/O mouth, even three groups of 8 bits I/O mouth to mouth, PB mouth and PA PC mouth. They are divided into two groups 12 I/O mouth, A group including port A and C mouth (high four, PC4 ~ PC7), including group B and C port B mouth (low four, PC0 ~ PC3). A group can be set to give basic I/O mouth, flash control (STROBE) I/O flash controlled, twoway I/O3 modes, Group B can only set to basic I/O or flash controlled the I/O, and these two modes of operation mode entirely by controlling registers control word decision. 2. 8255 pins efficacy: (1). RESET: RESET input lines, when the input outside at high levels, all internal registers (including control registers) were removed, all I/O ports are denoting input methods. (2). CS: chip choose a standard lamp line 1, when the input pins for low levels, namely/CS = 0, said chip is selected, allow 8255 and CPU for munications, / CS = 1, 15 8255 cannot with CPU do data transmission. (3). RD: read a standard lamp line 1, when the input pins for low levels, namely/RD = 0 and/CS = 0, allow 8255 through the data bus to the CPU to send data or state information, namely the CPU 8255 read from the information or data. (4). The WR: write a standard lights, when the input pins for low levels, namely/WR = 0 and/CS = 0, allows the CPU will data or control word write 8255. (5). D7: three states D0 ~ twoway data bus, 8255 and CPU data transmission channel, when the CPU execution input/output instruction, through its realization 8 bits of data read/write operation, control characters and status information transmitted through the data bus. (6). PA0 ~ PA7: port A input and output lines, A 8 bits of data output latches/buffers, an 8 bits of data input latches. (7). PB0 ~ PB7: port B input and output lines, a 8 bits of I/O latches, an 8 bits of input and output buffer. (8). PC0 ~ PC7: port C input and output lines, a 8 bits of data output latches/buffers, an 8 bits of data input buffer. Port C can through the way of working setting into two four ports, every 4 digit port contains A 4 digit latches, respectively with the port A and port B cooperate to use, can be used as control standard lights output or state standard lights input ports. (9). A0, A1: address selection line, used to select the PA 8255 mouth, PB mouth, PC mouth and controlling registers. When A0=0, A1= 0, PA mouth be chosen。 圖 5 車(chē)輛行駛狀態(tài)圖 依據(jù)上述的車(chē)輛行駛的狀態(tài)圖，可以列出各個(gè)路口燈的邏輯表，由于相向的燈的狀態(tài)圖是一樣的，所以只需寫(xiě)出相鄰路口的燈的邏輯表；根據(jù) 行駛狀態(tài)圖 可以看出，相鄰路口的燈它們的狀態(tài)在相位上相差 180176。 圖 3 十字路口車(chē)道形狀圖 圖 4 為直方圖，上邊為北路口燈，右邊為東路口燈，下邊為南路口燈，左邊為西路口燈。它不顧當(dāng)前道路上交通車(chē)輛數(shù)的實(shí)際情況變化，其最大的缺陷就在于當(dāng)路況發(fā)生變化時(shí)，不能滿(mǎn)足司機(jī)與路人的實(shí)際需 9 要，輕者造成時(shí)間上的浪費(fèi)，重者直接導(dǎo)致交通堵塞，導(dǎo)致城市交通效率的下降。在交通燈的通行與禁止時(shí)間控制顯示中，通常要么東西、南北兩方向各 50 秒；要么根據(jù)交通規(guī)律，東西方向 60 秒，南北方向 40 秒，時(shí)間控制都是固定的。 十字路口交通燈設(shè)計(jì)中采用的一般思路 十字道口的紅綠燈是交通法規(guī)的無(wú)聲命令，是司機(jī)和行人的行 為準(zhǔn)則。該方法節(jié)省硬件成本，切能夠使讀者在定時(shí)器 /計(jì)數(shù)器的使用、中斷及程序設(shè)計(jì)方面得到鍛煉與提高。有嚴(yán)格的低溫要求。與光導(dǎo)探測(cè)器比較，光伏探測(cè)器背影限探測(cè)率大于 40％；不需要外加偏置電場(chǎng)和負(fù)載電阻，不消耗功率，有高的阻抗。 (2) 光伏型：主要是 p－ n 結(jié)的光生伏特效應(yīng)。入射光子激發(fā)均勻半導(dǎo)體中的價(jià)帶電子越過(guò)禁帶進(jìn)入導(dǎo)帶并在價(jià)帶留下空穴，引起電導(dǎo)增加，為本 征光電導(dǎo)。因?yàn)檩d流子不逸出體外，所以稱(chēng)內(nèi)光電效應(yīng)。 7 MAX692 是微系統(tǒng)監(jiān) 控電路芯片，具有后備電池切換、掉電判別、看門(mén)狗監(jiān)控等功能。 交通信號(hào)控制類(lèi)型 交通信號(hào)控制的目的有三點(diǎn)：第一，在時(shí)間上和空間上分隔交叉口不同方向的車(chē)流，控制車(chē)流的運(yùn)行秩序；第二，使在平面交叉的道路網(wǎng)絡(luò)上人和物的運(yùn)輸達(dá)到最高效率；第三，為道路使用者提供必要的信息，幫助他們有效地使用交通設(shè)施。所有段的發(fā)光強(qiáng)度值中最大值與最小值之 比為發(fā)光強(qiáng)度比。 （ 3）按結(jié)構(gòu)分，有反射罩式、單條七段式及單片集成式。通常把數(shù)碼管、符號(hào)管、米字管共稱(chēng)筆畫(huà)顯示器，而把筆畫(huà)顯示器和矩陣管統(tǒng)稱(chēng)為字符顯示器。 當(dāng) A0=0,A1=0 時(shí) ,PA 口被選擇； 當(dāng) A0=0,A1=1 時(shí) ,PB 口被選擇； 當(dāng) A0=1,A1=0 時(shí) ,PC 口被選擇； 當(dāng) A0=1,A1=1 時(shí) ,控制寄存器被選擇。 (7).PB0~PB7：端口 B 輸入輸出線(xiàn)，一個(gè) 8 位的 I/O 鎖存器，一個(gè) 8 位的輸入輸出緩沖器。 (3).RD：讀旌旗燈號(hào)線(xiàn)，當(dāng)這個(gè)輸入引腳為低電平時(shí) ,即 /RD=0 且 /CS=0 時(shí) ,允許8255 通過(guò)數(shù)據(jù)總線(xiàn)向 CPU 發(fā)送數(shù)據(jù)或狀態(tài)信息，即 CPU 從 8255 讀取信息或數(shù)據(jù)。它們的值一直到下一個(gè)周期被電路捕捉下來(lái)。定時(shí)器 2可以被寄存器 T2CON 中的 TF2 和 EXF2 的或邏輯觸發(fā)。 位是不可用的。如圖 1 為 8051 引腳分配圖。 AT89C51 具有以下標(biāo)準(zhǔn)功能： 8k 字節(jié) Flash， 256 字節(jié) RAM， 32 位 I/O 口線(xiàn)，看門(mén)狗定時(shí)器， 2 個(gè)數(shù)據(jù)指針，三個(gè) 16 位定時(shí)器 /計(jì)數(shù)器，一個(gè) 6 向量 2 級(jí)中斷結(jié)構(gòu)，全雙工串行口，片內(nèi)晶振及時(shí)鐘電路。 關(guān)于 AT89C51 (1)功能特征描述 : 3 AT89C51 是一種低功耗、高性能 CMOS8 位微控制器，具有 8K 在系統(tǒng)可編程Flash 存儲(chǔ)器。例如：在冶金工業(yè)、化工生產(chǎn)、電力工程、造紙行業(yè)、機(jī)械制造和食品加工等諸多領(lǐng)域中，人們都需要對(duì)交通進(jìn)行有序的控制。 在