【正文】 畢業(yè)（設計）論文題目：基于 Verilog 的 FSK 調(diào)制器的設計與實現(xiàn) 湖北經(jīng)濟學院本科畢業(yè)（設計）論文目 錄摘 要 ...............................................................................................................................................1ABSTRACT..................................................................................................................................................2一、 前言 .............................................................................................................................................3（一）課題簡介 ...........................................................................................................................................3（二）文獻綜述 ...........................................................................................................................................3二、系統(tǒng)的總體方案設計 .........................................................................................................................8（一）設計要求 ...........................................................................................................................................8（二）設計原理及方案 ...............................................................................................................................8三、各單元電路設計 ..............................................................................................................................14（一）DDS 整體結(jié)構設計 .........................................................................................................................14（二）調(diào)制器 .............................................................................................................................................17(三)數(shù)字基帶信號 ......................................................................................................................................18四、軟件設計及仿真 ..............................................................................................................................19（一）硬件邏輯電路設計流程 .................................................................................................................19（二）DDS 技術軟件設計與仿真 .............................................................................................................21（三）選擇器仿真 .....................................................................................................................................24（四）FSK 調(diào)制器軟件仿真 ......................................................................................................................24(五)數(shù)字基帶信號仿真 ...............................................................................................................................24五、系統(tǒng)調(diào)試/硬件測試 .........................................................................................................................26（一）硬件調(diào)試方法 .................................................................................................................................26（二）系統(tǒng)的硬件驗證及聯(lián)調(diào) .................................................................................................................27小 結(jié) .............................................................................................................................................30致 謝 .............................................................................................................................................31參考文獻 .................................................................................................................................................32附 錄 .................................................................................................................................................33湖北經(jīng)濟學院本科畢業(yè)（設計）論文1摘 要FSK（Frequencyshift keying）是信息傳輸中使用得較早的一種調(diào)制方式，它實現(xiàn)起來較容易,抗噪聲與抗衰減的性能較好，在中低速數(shù)據(jù)傳輸中得到了廣泛的應用。而 DDS（Direct Digital Synthesizer）是直接數(shù)字式頻率合成器的英文縮寫，和 DSP（digital signal processor）——數(shù)字信號處理一樣，DDS 是一種很重要的數(shù)字化技術。與傳統(tǒng)的頻率合成器相比，DDS 的優(yōu)點有低成本、低功耗、高分辨率和快速轉(zhuǎn)換時間，它廣泛地運用在電信與電子儀器領域，是實現(xiàn)設備全數(shù)字化的一個關鍵技術。而本課題設計的基于 Verilog 的 FSK 調(diào)制器，就是采用 EDA 技術，以FPGA 為核心，在 DDS 技術的基礎上實現(xiàn) FSK 調(diào)制器的設計。設計中用 FPGA 芯片完成各種時序邏輯控制、計數(shù)功能。在 Quartus Ⅱ平臺上，用 Verilog HDL 語言編程完成了 FPGA 的軟件設計、編譯、調(diào)試、仿真和下載，在FPGA 上進行硬件的測試。關鍵詞: FSK 調(diào)制器 DDS FPGA Quartus Ⅱ 湖北經(jīng)濟學院本科畢業(yè)（設計）論文2ABSTRACT FSK (Frequencyshift keying) may be used for transmission of information of a modulation earlier, it is easier to implement, preferably antiantinoise and attenuation properties, has been widely used in lowspeed data transmission. And a DSP (digital signal processor) as digital signal processing, DDS is a very important digital technology. DDS (Direct Digital Synthesizer) yes yes direct digital frequency synthesizer abbreviation. Compared with the conventional frequency synthesizer, DDS has the advantage of lowcost, lowpower, high resolution and fast conversion time, it is widely used in the field of telemunications and electronic equipment, is to achieve full digital equipment is a key technology. The design of this project Verilogbased FSK modulator, is the use of EDA technology to FPGA as the core, FSK modulator based on DDS technology design. Complete a variety of designs using FPGA chip timing control logic, counting function. On the Quartus Ⅱ platform with Verilog HDL language programming plete FPGA design software, piling, debugging, simulation and downloading, after the FPGA hardware tests.Keywords: FSK modulator DDS FPGA Quartus Ⅱ 湖北經(jīng)濟學院本科畢業(yè)（設計）論文3一、 前言（一）課題簡介直接數(shù)字式頻率合成 DDS 技術是近年來發(fā)展起來的一種新的頻率合成技術。其主要優(yōu)點是相對帶寬很寬、頻率轉(zhuǎn)換時間極短（可小于 20ns）、頻率分辨率很高（典型值為 ）、全數(shù)字化結(jié)構便于集成、輸出相位連續(xù)、頻率、相位和幅度均可實現(xiàn)程控。本設計在采用 Verilog HDL 語言實現(xiàn) DDS 信號源的基礎上,實現(xiàn) FSK 調(diào)制器的設計。，了解基于 DDS 的原理和實現(xiàn)方法； Verilog HDL 語言實現(xiàn) DDS 信號源,然后利用 DDS 技術實現(xiàn) FSK 調(diào)制器的設計，并且在 FPGA 上進行硬件測試；（二）文獻綜述 在當今時代，計算機、電子及信息技術的飛速發(fā)展使得多種類、高精度、高分辨率、寬頻帶的信號源在空間通信、雷達測量、遙控遙測、無線電定位、衛(wèi)星導航和數(shù)字通信等領域中的作用越來越大。它本身