外文翻譯---基于dds參數(shù)可調(diào)諧波信號發(fā)生器的研究(已修改)
2025-01-30 16:34 本頁面
【正文】 附錄AResearch of Parameter Adjustable Harmonic Signal Generator Based on DDSLI WeiCollege of Computer and Information Engineering Hohai UniversityChangzhou, 213022, China liwei_2142@ZHANG JinboCollege of Computer and Information Engineering Hohai University Changzhou, 213022, China zhangjb@AbstractHarmonic signal generator whose frequency, phase and harmonic proportion are adjustable is designed for the detecting equipment of power system. The principle of DDS and the design requirement are introduced. Then the algorithm of ROM pression based on the symmetry of sine wave is expounded. Finally, using Altera FPGA, the detail design of the whole system is presented and test waveforms are given. Test results indicate that the system fulfils the design requirements.1. IntroductionAn ideal power system supplies power with sine wave, but the practical waveform of power supply often has many harmonic ponents. The basic reason of harmonic is that the power system supplies power to the electrical equipment with nonlinear characteristic. These nonlinear loads feed higher harmonic back to the power supply, and make the waveform of current and voltage in power system produce serious distortion. In the detection field of power system, standard signal generators which can simulate the power harmonic are highly needed to calibrate the power detecting equipment, such as phase detector, PD detector, and so on. So the research of parameter adjustable harmonic signal generator provides the exact basis for the stable operation of power detecting equipment, and has great economic benefit and social value.2. Principle of direct digital synthesisDirect digital synthesis (DDS) is a new frequency synthesis technology which directly synthesizes waveform on the basis of phase. Using the relationship between phase and amplitude, the phase of waveform is segmented and assigned relevant addresses. In each clock period, these addresses are extracted and the relevant amplitudes are sampled. The envelope of these sampled amplitudes is the expected waveform. If the clock frequency is constant, the frequency of output signal is adjustable with different extracted steps of addresses.DDS is posed of phase accumulator, ROM table, DAC and LPF. In each clock period, the output of phase accumulator is accumulated with frequency control word, and high Lbit of the output are used as address to query the ROM table. In the ROM, these addresses are converted to the sampled amplitudes of the expected waveform. Then DAC converts the sampled amplitudes to ladder wave. In the LPF, the ladder wave is smoothed, and the output is the continuous analog waveform.Suppose that the clock frequency is fc, frequency control word is K, phase accumulator is Nbit, then output frequ
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