【正文】 ICL7135 4 1/2 Digit, BCD Output, A/D Converter The Intersil ICL7135 precision A/D converter, with its multiplexed BCD output and digit drivers, bines dualslope conversion reliability with +1 in 20,000 count accuracy and is ideally suited for the visual display DVM/DPM market. The full scale capability, autozero, and autopolarity are bined with true ratiometric operation, almost ideal differential linearity and true differential input. All necessary active devices are contained on a single CMOS lC, with the exception of display drivers, reference, and a clock. The ICL7135 brings together an unprecedented bination of high accuracy, versatility, and true economy. It features autozero to less than 10181。 V, zero drift of less than 1181。V/℃ , input bias current of 10pA (Max), and rollover error of less than one count. The versatility of multiplexed BCD outputs is increased by the addition of several pins which allow it to operate in more sophisticated systems. These include STROBE , OVERRANGE , UNDERRANGE , RUN/HOLD and BUSY lines, making it possible to interface the circuit to a microprocessor or UART. Features * Accuracy Guaranteed to+1 Count Over Entire 20200 Counts ( Full Scale) * Guaranteed Zero Reading for 0V Input * 1pA Typical Input Leakage Current * True Differential Input * True Polarity at Zero Count for Precise Null Detection * Single Reference Voltage Required * Over range and Under range Signals Available for AutoRange Capability * All Outputs TTL Compatible * Blinking Outputs Gives Visual Indication of Over range * Six Auxiliary Inputs/Outputs are Available for Interfacing to UARTs , Microprocessors, or Other Circuitry * Multiplexed BCD Outputs * PbFree Available (RoHS Compliant) Detailed Description Analog Section Each measurement cycle is divided into four phases. They are (1) autozero (AZ), (2) signalintegrate (INT), (3) deintegrate (DE) and (4) zerointegrator (Zl). AutoZero Phase During autozero, three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the autozero capacitor CAZ to pensate for offset voltages in the buffer amplifier, integrator, and parator. Since the parator is included in the loop, the AZ accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10181。V. Signal Integrate Phase During signal integrate , the autozero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide mon mode range。 within one volt of either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct monmode voltage. At the end of this phase, the polarity of the integrated signal is latched into the polarity F/F. DeIntegrate Phase The third phase is deintegrate or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the out put to return to zero is proportional to the input signal. Specifically the digital reading displayed is: Zero Integrator Phase The final phase is zero integrator. First, input low is shorted to analog COMMON. Second, a feedback loop is closed around the system to input high to cause the integrator output to return to zero. Under normal condition, this phase lasts from 100 to 200 clock pulses, but after an over range conversion, it is extended to 6200 clock pulses. Differential Input The input can accept differential voltages anywhere within the mon mode range of the input amplifier。 or specifically from below the positive supply to 1V above the negative supply. In this range the system has a CMRR of 86dB typical. However, since the integrator also swings with the mon mode voltage, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive monmode voltage with a near full scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive mon mode voltage. For these critical applications the integrator swing can be reduced to less than the remended 4V full scale swing with some loss of accuracy. The integrator output can swing within of either supply without loss of linearity. Analog COMMON Analog COMMON is used as the input low re