畢業(yè)設(shè)計(jì)外文翻譯--89c51單片機(jī)-文庫吧
2024-11-12 08:09 本頁面
【正文】 Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the highorder address bits and some control signals during Flash programming and verification. Port 3 is an 8bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves Port Pin Alternate Functions MOSI (used for InSystem Programming) MOSO (used for InSystem Programming) SCK(used for InSystem Programming) 中北大學(xué) 2021 屆畢業(yè)設(shè)計(jì)中英文翻譯 3 the functions of various special features of the AT89S51, as shown in the following table. 3 Memory Organization MCS51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed. Program Memory If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S51, if EA is connected to VCC, program fetches to addresses 0000H through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory. Data Memory The AT89S51 implements 128 bytes of onchip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space. 4 Watchdog Timer (Onetime Enabled with Resetout) The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST Port Pin Alternate Functions RXD(serial input port) TXD(serial output port) INT0(external interrupt 0) INT1(external interrupt 1) T0(timer 0 external input) T1(timer 1 external input) WR(external data memory write strobe) RD(external data memory read strobe) 中北大學(xué) 2021 屆畢業(yè)設(shè)計(jì)中英文翻譯 4 register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin. Using the WDT To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every
公司管理相關(guān)推薦
鄂ICP備17016276號(hào)-1