【正文】 , and serial I/O. All of these functions and the CPU are packaged on a single chip. A control code sets the display format, position, and four attributes: color, italics, underline, and flash. The subsequent characters are positioned as specified in the OSD Display RAM with these attributes. The decoded data is stored in the display RAM, then is converted to the R, G, B, and BL signals by using the Generator ROM information. The R, G, B, and BL signals are synchronized to the vertical and horizontal synchronization signals, and to the dot clock generated by the builtin circuit. These signals carry the attribute information and font data that will be displayed on the screen according to current display format. 3. Closed Caption OnScreen Display Function Circuit Configuration The Closed Caption Onscreen Display function (OSD) consists of the control block, Display RAM, Character Generator ROM, output block and oscillation circuit. The control block consists of the mode and timing control circuit, the vertical position control circuit, and the horizontal position control circuit. This block controls the access timing of the Display RAM and 第 5 頁 共 20 頁 displays output in various display modes. The closed caption data in each field, which is level sliced and captured by the LSI, is serially transferred to the Data Register of this microcontroller. The trailing edge of the signal generates an interrupt. This interrupt causes the software to judge the fields, check data parity, and decode caption data. The data length of the Display RAM is eight bits. To support the Caption Text mode and reduce the burden on software under OnScreen Display control, the Display RAM is adaptable to a fullscreen size. Each row consists of one column used for the initial attribute value, and 32 columns used for the display area. The Character Generator ROM has a capacity of 112 preset character fonts in Closed Caption format and 16 character fonts. The output block control character output according to the display format used in each mode. Existing Display RAM Architecture If the timing of onscreen display is synchronized to the CPU clock, jitter occurs horizontally. This is why that timing must be synchronized to the deflection system. Therefore, a dualport RAM structure is generally used in the Display RAM for the TV control microcontroller to enable asynchronous access from the CPU and OSD circuit. However, a dualport RAM requires more space and increases cost, therefore； a smallercapacity Display RAM is usually provided to solve this problem. In this case, the Display RAM can hold only the data for a small part of the screen. To display an entire screen, the Display RAM data must be changed each time the display position is moved to another group of rows. This requires the display control routine of the program to be 第 6 頁 共 20 頁 executed very quickly. Therefore, program has to be designed very carefully with special design techniques, thus, program will be plicated and it takes longer design period. Display RAM Architecture of this Microcontroller To implement caption mode display, at least 256 bytes of memory are necessary to store the data. In the fullscreen Text Mode, 480 bytes of memory are necessary to store the data. This amount of memory must be prepared either as display memory or data memory. Based on our study and examination, we believe that the Display RAM architecture described below facilitates the most efficient implementation possibility: (1) Provide the RAM with fullscreen capability and the display data memory functions. (2) Employ the single port structure of this RAM that can be accessed simultaneously from the CPU and display control circuit with no restrictions. These measures solve the problems described in Section and minimize the cost of providing Text Mode capability. 4. Single Port RAM implementation Timing allocation on single port Display RAM Display RAM is accessed through the row address and column address synchronized by the CPU clock. For access from the CPU, the row address is specified by the row address register。 the column address is specified by the column address register. For access from the caption display circuit, the row address of the Display RAM is determined by the vertical position of the character to be displayed. The column address of the Display RAM 第 7 頁 共 20 頁 is determined by the horizontal position of the character to be displayed. The 32 characters have to be displayed in one line and each character consists of an eightdot horizontal attribute specification code according to the mode used. Italics, flash, underline, and character color are specified in the caption and text modes. Character background color and character color are specified in 16line OSD mode and 8line OSD mode. 5. Other Features in OSD Mode The following OSD mode features are also provided: 8 character colors 8 character background/fringe colors 8 full screen background colors Normalsize, doublesize, and quadruplesize ch