外文翻譯---基于dds參數(shù)可調(diào)諧波信號(hào)發(fā)生器的研究-文庫(kù)吧
2025-01-03 16:34 本頁(yè)面
【正文】 ency is fout=(K/2N)fc, frequency resolution is Δfmin=fc/2N. According to the Nyquist Sample Criterion, output frequency upper limit is fmax. Because of the nonideal characteristic of LPF, output frequency upper limit of DDS is fmax=.3. Scheme design. Design requirementsThe goal of the system is to design a harmonic signal generator, whose frequency, phase and harmonic proportion are adjustable. The output waveform is posed of fundamental wave, 3th harmonic, 5th harmonic and 7th harmonic. Frequency resolution is 1Hz. The adjustable range of initial phase is 0~2π and its resolution is 1o. The adjustable range of harmonic proportion is 0~50% and its resolution is 1%. According to the design requirements, system clock frequency is 15MHz and phase accumulator is 24bit. In order to make the most of EAB, 2118 bits ROM table is adopted. 11bit phase control word is used to meet the requirement of initial phase resolution. 7bit proportion control word is adopted to realize the setting of harmonic proportion.. Algorithm of ROM pressionAs is known, phase truncation error is the main factor of output waveform distortion. To avoid this, the ROM size must be exponentially increased, however the EAB of FPGA is limited. So the algorithm of ROM pression based on the symmetry of sine wave is adopted in the system. Sine wave of one period is divided into 4 sections: [0~π/2] 、[π/2~π] 、[π~3π/2] 、[3π/2~2π]. Using the symmetry of sine wave, sampled amplitudes of the first section are stored in the ROM table. By address conversion and amplitude conversion, sampled amplitudes of one period sine wave can be generated. By this means, the ROM size is a quarter of the previous size. In the same ROM, sampling points can be increased by 4 times with this method.Sampled amplitudes of quarter wave are stored in the ROM table. The output address of phase accumulator is (L+2)bit. The low Lbit are used to query the ROM table while the high 2bit are used to identify phase sections. When the highest bit is 1, the output of ROM table should be symmetrically converted by the amplitude convertor. When the second highest bit is 1, the Lbit address should be symmetrically converted by the address convertor.4. System design based on FPGAThe system can be divided into two function modules: sine wave generation module and harmonic synthesis module. Sine wave generation module is the key part of the system. It can be divided into phase accumulator module and ROM pression module . Altera FPGA EP2C5Q208C8 is adopted as the core ponent of the system. VHDL is used to program the whole system. Compilation and simulation are implemented in Quartus Ⅱ.. Sine wave generation modulephase accumulator module is posed of 24bit accumulator and 11bit adder. Under the control of
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