introductiontocmosvlsidesignlogicaleffort-文庫吧
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【正文】 p = gh + p E l e c t r i c a l E f f o r t :h = Cout / CinNormalized Delay: dIn v e r t e r2 i n p u tN A N Dg =p =d =g =p =d =0 1 2 3 4 50123456CMOS VLSI Design Logical Effort Slide 12 Delay Plots d = f + p = gh + p ? What about NOR2? E l e c t r i c a l E f f o r t :h = Cout / CinNormalized Delay: dIn v e r t e r2 i n p u tN A N Dg = 1p = 1d = h + 1g = 4 / 3p = 2d = ( 4 / 3 ) h + 2E f f o r t D e l a y : fP a r a s i t i c D e l a y : p0 1 2 3 4 50123456CMOS VLSI Design Logical Effort Slide 13 Computing Logical Effort ? DEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current. ? Measure from delay vs. fanout plots ? Or estimate by counting transistor widths A YABYABY121 12 22244Cin = 3g = 3 / 3Cin = 4g = 4 / 3Cin = 5g = 5 / 3CMOS VLSI Design Logical Effort Slide 14 Catalog of Gates Gate type Number of inputs 1 2 3 4 n Inverter 1 NAND 4/3 5/3 6/3 (n+2)/3 NOR 5/3 7/3 9/3 (2n+1)/3 Tristate / mux 2 2 2 2 2 XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8 ? Logical effort of mon gates CMOS VLSI Design Logical Effort Slide 15 Catalog of Gates Gate type Number of inputs 1 2 3 4 n Inverter 1 NAND 2 3 4 n NOR 2 3 4 n Tristate / mux 2 4 6 8 2n XOR, XNOR 4 6 8 ? Parasitic delay of mon gates – In multiples of pinv (?1) CMOS VLSI Design Logical Effort Slide 16 Example: Ring Oscillator ? Estimate the frequency of an Nstage ring oscillator Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay: d = Frequency: fosc = CMOS VLSI Design Logical Effort Slide 17 Example: Ring Oscillator ? Estimate the frequency of an Nstage ring oscillator Logical Effort: g = 1 Electrical Effort: h = 1 Parasitic Delay: p = 1 Stage Delay: d = 2 Frequency: fosc = 1/(2*N*d) = 1/4N 31 stage ring oscillator in mm process has frequency of ~ 200 MHz CMOS VLSI Design Logical Effort Slide 18 Example: FO4 Inverter ? Estimate the delay of a fanoutof4 (FO4) inverter Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay: d = dCMOS VLSI Design Logical Effort Slide 19 Example: FO4 Inverter ? Estimate the delay of a fanoutof4 (FO4) inverter Logical Effort: g = 1 Electrical Effort: h = 4 Parasitic Delay: p = 1 Stage Delay: d = 5 dThe FO4 delay is about 200 ps in mm process 60 ps in a 180 nm process f/3 ns in an f mm process CMOS VLSI Design Logical Effort Slide 20 Multistage Logic Networks ? Logical effort generalizes to multistage works ? Path Logical Effort ? Path Electrical Effort ? Path
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