surveyofdigitalsignalprocessors-文庫(kù)吧
2025-09-08 14:57 本頁(yè)面
【正文】 What Makes a DSP a DSP? Hard RealTime ? SingleCycle MAC ? Multiple Execution Units ? Custom Data Path ? High Bandwidth (Flat) Memory SubSystems ? Dual Access Memory ? Efficient ZeroOverhead Looping ? Short Pipeline ? High Bandwidth I/O ? Specialized Instruction Sets ? Low Latency Interrupts ? Sophisticated DMA ? No Speculation ? RTOS Soft RealTime (Application Processor) ? SingleCycle MAC ? Multiple Execution Units ? Custom Data Path ? L1D$, L1I$, L2$ with MMU ? Speculative Fetching and Branching ? Virtual Memory ? Protected Memory ? Virtual Machines ? Semaphores ? Context Save and Restore ? Threading: SMT, IMT ? Efficient ZeroOverhead Looping ? Short Pipeline ? High Bandwidth I/O ? Specialized Instruction Sets ? Low Latency Interrupts ? Sophisticated DMA ? O/S Single Cycle MAC ? MAC’s Typically Determine DSP Performance and Pipeline Length (EX) ? Most DSP’s Have 28 MAC Units ? MAC’s Typically Operate in Both a Scalar and Vector Mode Multiple Instruction Units ? VLIW Architectures Driving ILP ? Typically Instruction Units ? MUnit MAC ? SUnit Shift ? LUnit ALU ? DUnit – Load/Store ? Industry Has Converged on a ILP of ~8 DDATA_I2 (load data) D2 D S1 S2 M1 D S1 S2 D1 D S1 S2 DDATA_I1 (load data) 2X 1X L 1 S1 S1 S2 DL SL SL D DL S2 S1 D M2 L2 S2 S2 D DL SL SL D DL S2 S1 S1 S2 D S1 Registers B0 B15 Registers A0 A15 High Bandwidth Memory SubSystems ? Multiple LoadStore Units Required to Feed Data Path ? Tightly Coupled Memory is Typically Dual Ported ? Harvard Architecture is Heavily Banked Central Arithmetic Logic Unit EXTERNAL MEMORY M U X INTERNAL MEMORY M U X E S P
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