光伏發(fā)電逆變器畢業(yè)論文中英文資料外文翻譯文獻(xiàn)-文庫吧
2024-08-13 07:16 本頁面
【正文】 ce (SPI) module ? PLLbased clock module ? Digital I/O and shared pin functions ? External memory interfaces (‘LF2407 only) ? Watchdog (WD) timer module Event manager modules (EVA, EVB) The eventmanager modules include generalpurpose (GP) timers, fullpare/PWM units, capture units, and quadratureencoder pulse (QEP) circuits. EVA‘s and EVB‘s timers, pare units, and capture units function identically. However, timer/unit names differ for EVA and EVB. Table 1 shows the module and signal names used. Table 1 shows the features and functionality available for the eventmanager modules and highlights EVA nomenclature. Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB starting at 7500h. The paragraphs in this section describe the function of GP timers, pare units, capture units, and QEPs using EVA nomenclature. These paragraphs are applicable to EVB with regard to function—however, module/signal names would differ. Table 1. Module and Signal Names for EVA and EVB EVENT MANAGER MODULES EVA MODULE SIGNAL EVB MODULE SIGNAL GP Timers Timer 1 Timer 2 T1PWM/T1CMP T2PWM/T2CMP Timer 3 Timer 4 T3PWM/T3CMP T4PWM/T4CMP Compare Units Compare 1 Compare 2 PWM1/2 PWM3/4 Compare 4 Compare 5 PWM7/8 PWM9/10 畢業(yè)論文 4 Compare 3 PWM5/6 Compare 6 PWM11/12 Capture Units Capture 1 Capture 2 Capture 3 CAP1 CAP2 CAP3 Capture 4 Capture 5 Capture 6 CAP4 CAP5 CAP6 QEP QEP1 QEP2 QEP1 QEP2 QEP3 QEP4 QEP3 QEP4 External Inputs Direction External Clock TDIRA TCLKINA Direction External Clock TDIRB TCLKINB 畢業(yè)論文 5 畢業(yè)論文 6 Generalpurpose (GP) timers There are two GP timers: The GP timer x (x = 1 or 2 for EVA。 x = 3 or 4 for EVB) includes: ? A 16bit timer, up/downcounter, TxCNT, for reads or writes ? A 16bit timerpare register, TxCMPR (doublebuffered with shadow register), for reads or writes ? A 16bit timerperiod register, TxPR (doublebuffered with shadow register), for reads or writes ? A 16bit timercontrol register,TxCON, for reads or writes ? Selectable internal or external input clocks ? A programmable prescaler for internal or external clock inputs ? Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer pare, and period interrupts ? A selectable direction input pin (TDIR) (to count up or down when directional up/downcount mode is selected) The GP timers can be operated independently or synchronized with each other. The pare register associated with each GP timer can be used for pare function and PWMwaveform generation. There are three continuous modes of operations for each GP timer in up or up/downcounting operations. Internal or external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the time base for the other eventmanager submodules: GP timer 1 for all the pares and PWM circuits, GP timer 2/1 for the capture units and the quadraturepulse counting operations. Doublebuffering of the period and pare registers allows programmable change of the timer (PWM) period and the pare/PWM pulse width as needed. Fullpare units There are three fullpare units on each event manager. These pare units use GP timer1 as the time base and generate six outputs for pare and PWMwaveform generation using programmable deadband circuit. The state of each of the six outputs is configured independentl
環(huán)評公示相關(guān)推薦
鄂ICP備17016276號-1