【正文】 xternal program memory PSEN is activated twiceeach machine cycle except that two PSEN activations are skipped during each access toexternal data memory EAVPPExternal Access Enable EA must be strapped to GND in order to enable the deviceto fetch code from external program memory locations starting at 0000H up to FFFFHNote however that if lock bit 1 is programmed EA will be internally latched onresetEA should be strapped to VCC for internal program executions This pin alsreceives the 12volt programming enable voltage VPP during Flash programming forparts that require 12volt VPP XTAL1Input to the inverting oscillator amplifier and input to the internal clock operatingcircuit XTAL2 Output from the inverting oscillator amplifierOscillator CharacteristicsXTAL1 and XTAL2 are the input and output respectively of an inverting amplifierwhich can be configured for use as an onchip oscillator as shown in Figure 1 Either aquartz crystal or ceramic resonator may be used To drive the device from an externalclock source XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2There are no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is through a dividebytwo flipflop but minimum and imum voltage high and low time specifications must be observed Idle Mode In idle mode the CPU puts itself to sleep while all the onchip peripherals remain active The mode is invoked by software The content of the onchip RAM and all the special functions registers remain unchanged during this mode The idle mode can be terminated by any enabled interrupt or by a hardware reset It should be noted that when idle is terminated by a hard ware reset the device normally resumes program execution from where it left off up to two machine cycles before the internal reset algorithm takes control Onchip hardware inhibits access to internal RAM in this event but access to the port pins is not inhibited To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory Powerdown Mode In the powerdown mode the oscillator is stopped and the instruction that invokes powerdown is the last instruction executed The onchip RAM and Special Function Registers retain their values until the powerdown mode is terminated The only exit from powerdown is a hardware reset Reset redefines the SFRs but does not change the onchip RAM The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilizeThe AT89C51 code memory array is programmed bytebybyte in either programming mode To program any nonblank byte in the onchip Flash Memory the entire memory must be erased using the Chip Erase Mode 2 Programming Algorithm Before programming the AT89C51 the address data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4 To program the AT89C51 take the following steps1 Input the desired memory location on the address lines2 Input the appropriate data byte on the data lines 3 Activate the correct bination of control signals 4 Raise EAVPP to 12V for the highvoltage programming mode 5 Pulse ALEPROG once to program a byte in the Flash array or the lock bits The bytewrite cycle is selftimed and typically takes no more than 15 ms Repeat steps 1 through 5 changing the address and data for the entire array or until the end of the object file is reached Data Polling The AT89C51 features Data Polling to indicate the end of a write cycle During a write cycle an attempted read of the last byte written will result in the plement of the written datum on PO7 Once the write cycle has been pleted true data are valid on all outputs and the next cycle may begin Data Polling may begin any time after a write cycle has been initiated 21ReadyBusy The progress of byte programming can also be monitored by the RDYBSY output signal P34 is pulled low after ALE goes high during programming to indicate BUSY P34 is pulled high again when programming is done to indicate READY Program Verify If lock bits LB1 and LB2 have not been programmed the programmed code data can be read back via the address and data lines for verification The lock bits cannot be verified directly Verification of the lock bits i