【正文】 e timers can be used to count or time external events that drive the Timer input Stellaris? GeneralPurpose Timer Module (GPTM) contains three GPTM blocks (Timer0, Timer1,and Timer 2). Each GPTM block provides two 16bit timers/counters (referred to as TimerA andTimerB) that can be configured to operate independently as timers or event counters, or configuredto operate as one 32bit timer or one 32bit RealTime Clock (RTC). In addition, timers can be used to trigger analogtodigital conversions (ADC). The ADC triggersignals from all of the generalpurpose timers are ORed together before reaching the ADC module,so only one timer should be used to trigger ADC events. The GPT Module is one timing resource available on the Stellaris? microcontrollers. Other timerresources include the System Timer (SysTick) and the PWM timer in thePWM module. The GeneralPurpose Timers provide the following features: ■ Three GeneralPurpose Timer Modules (GPTM), each of which provides two 16bittimers/counters. Each GPTM can be configured to operate independently: – As a single 32bit timer – As one 32bit RealTime Clock (RTC) to event capture – For Pulse Width Modulation (PWM) – To trigger analogtodigital conversions ■ 32bit Timer modes – Programmable oneshot timer – Programmable periodic timer – RealTime Clock when using an external clock as the input – Userenabled stalling when the controller asserts CPU Halt flag during debug – ADC event trigger ■ 16bit Timer modes – Generalpurpose timer function with an 8bit prescaler (for oneshot and periodic modes only) – Programmable oneshot timer – Programmable periodic timer – Userenabled stalling when the controller asserts CPU Halt flag during debug – ADC event trigger ■ 16bit Input Capture modes – Input edge count capture 270 September 04, 2021 Texas InstrumentsProduction Data GeneralPurpose Timers – Input edge time capture ■ 16bit PWM mode – Simple PWM mode with softwareprogrammable output inversion of the PWM signa Functional Description The main ponents of each GPTM block are two freerunning 16bit up/down counters (referredto as TimerA and TimerB), two 16bit match registers, two prescaler match registers, and two 16bitload/initialization registers and their associated control functions. The exact functionality of eachGPTM is controlled by software and configured through the register configures the GPTM using the GPTM Configuration (GPTMCFG) register,the GPTM TimerA Mode (GPTMTAMR) register and the GPTM TimerB Mode(GPTMTBMR) register. When in one of the 32bit modes, the timer can only act asa 32bit timer. However, when configured in 16bit mode, the GPTM can have its two 16bit timersconfigured in any bination of the 16bit GPTM Reset Conditions After reset has been applied to the GPTM module, the module is in an inactive state, and all controlregisters are cleared and in their default states. Counters TimerA and TimerB are initialized to0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load(GPTMTAILR) register (see page 296) and the GPTM TimerB Interval Load (GPTMTBILR) register. The prescale counters are initialized to 0x00: the GPTM TimerA Prescale(GPTMTAPR) register (see page 300) and the GPTM TimerB Prescale (GPTMTBPR) register. 32Bit Timer Operating Modes This section describes the three GPTM 32bit timer modes (OneShot, Periodic, and RTC) and theirconfiguration. The GPTM is placed into 32bit mode by writing a 0 (OneShot/Periodic 32bit timer mode) or a 1(RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTMregisters are concatenated to form pseudo 32bit registers. These registers include: ■ GPTM TimerA Interval Load (GPTMTAILR) register [15:0], ■ GPTM TimerB Interval Load (GPTMTBILR) register [15:0], ■ GPTM TimerA (GPTMTAR) register [15:0], ■ GPTM TimerB (GPTMTBR) register [15:0], In the 32bit modes, the GPTM translates a 32bit write access to GPTMTAILR into a write accessto both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is: GPTMTBILR[15:0]:GPTMTAILR[15:0] Likewise, a read access to GPTMTAR returns the value: GPTMTBR[15:0]:GPTMTAR[15:0] 32Bit OneShot/Periodic Timer Mode In 32bit oneshot and periodic timer modes, the concatenated versions of the TimerA and TimerBregisters are configured as a 32bit downcounter. The selection of oneshot or periodic mode isdetermined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register, and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register. When software writes the TAEN bit in the GPTM Control (GPTMCTL) register, theimer begins counting down from its preloaded value. Once the state is reached, thetimer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured tobe a oneshot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. Ifconfigured as a periodic timer, it continues counting. In addition to reloading the count value, the GPTM generates interrupts and triggers when it reachesthe state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status(GPTMRIS) register and holds it until it is cleared by writing the GPTM InterruptClear (GPTMICR) register. If the timeout interrupt is enabled in the GPTM InterruptMask (GPTMIMR) register (see page 290), the GPTM also sets the TATOMIS bit in the GPTM MaskedInterrupt Status (GPTMMIS) register (see page 293). The ADC trigger is enabled by setting theTAOTE bit in software reloads the GPTMTAILR register while the counter is running, the counter loads the newvalue on the next clock cycle and continues counting from the new the TASTALL bit in the GPTMCTL register is set, the timer freezes c