【正文】 ct sequence． Secondly， the system structure of the all digital direct sequence spread spectrum baseband system has been designed， finished the generating of the spread spectrum sequence， the input and spread spectrum of the information code． Mainly pleted relative de—spread spectrum towards the baseband spread spectrum signal and the design of several synchronized acqui sition circuit． Then these chips have been integrated on a largescale FPGA． Finally， partial VHDL program has been listed out， and the simulation of each module has been pleted by Quartus II ． Key Words： Spread Spectrum Communication； FPGA； Synchronization Acquisition 東華 理工大學(xué) III 目錄 第 1 章 緒論 .................................................................................................... 1 研究背景及意義 ..................................................................................................... 1 國(guó)內(nèi)外研究水平和發(fā)展趨勢(shì) .............................................................................. 2 ........................................................................................... 2 ........................................................................................... 2 擴(kuò)頻技術(shù)的研究現(xiàn)狀 ........................................................................................... 3 擴(kuò)頻技術(shù)的研究現(xiàn)狀 ................................................................................ 3 碼捕獲 ............................................................................................................ 3 .................................................................................................... 4 擴(kuò)頻技術(shù)的展望 .................................................................................................... 4 擴(kuò)頻技術(shù)的發(fā)展趨勢(shì) ................................................................................ 4 超寬帶技術(shù) ................................................................................................... 5 多載波調(diào)制技術(shù) .......................................................................................... 5 軟件無(wú)線電 ................................................................................................... 6 本論文的研究?jī)?nèi)容與結(jié)構(gòu) .................................................................................. 6 第 2 章 相關(guān)技術(shù)研究 ...................................................................................... 8 碼分多址（ CDMA）技術(shù)概述 ........................................................................ 8 碼分多址技術(shù)的概念 ................................................................................ 8 碼分多址技術(shù)基礎(chǔ)原理 ............................................................................ 8 擴(kuò)頻通信技術(shù) ........................................................................................................ 11 擴(kuò)頻通信的基本概念 ............................................................................... 11 搜索文檔 ：基于 FPGA 實(shí)現(xiàn) CDMA 擴(kuò)頻通信中同步系統(tǒng) IV 擴(kuò)頻通信的基本原理 ...............................................................................12 擴(kuò)頻通信的主要優(yōu)缺點(diǎn) ...........................................................................12 硬件描述語(yǔ)言和開(kāi)發(fā)平臺(tái) .................................................................................13 系統(tǒng)開(kāi)發(fā)語(yǔ)言 VHDL簡(jiǎn)介 .....................................................................13 Altera公司的 Quartus II .................................................14 FPGA設(shè)計(jì)流程 ...........................................................................................14 第 3 章 系統(tǒng)總體設(shè)計(jì)概述 ............................................................................ 16 系統(tǒng)總體設(shè)計(jì)思路 ...............................................................................................16 發(fā)送端的總體設(shè)計(jì) ...............................................................................................16 接受端的總體設(shè)計(jì) ...............................................................................................18 第 4 章 發(fā)送端的具體設(shè)計(jì)和實(shí)現(xiàn) ................................................................. 20 偽隨機(jī)碼序列發(fā)生器模塊的設(shè)計(jì)和實(shí)現(xiàn) .....................................................20 相加器模塊的設(shè)計(jì)和實(shí)現(xiàn) ..................................................................................21 設(shè)計(jì)思路 .......................................................................................................21 相加合成器 VHDL源代碼 .....................................................................22 發(fā)射端系統(tǒng)的功能仿真 .....................................................................................22 第 5 章 接收端的具體設(shè)計(jì)和實(shí)現(xiàn) ................................................................. 23 積分器 digint 模塊的設(shè)計(jì)和實(shí)現(xiàn) ....................................................................23 設(shè)計(jì)思路 .......................................................................................................23 積分器 digint源代碼 ................................................................................23 比較器 cmp127 模塊的設(shè)計(jì)和實(shí)現(xiàn) ................................................................24 設(shè)計(jì)思路 .......................................................................................................24 東華 理工大學(xué) V 比較器 cmp127的源代碼 .......................................................................25 分頻器 fd127 模塊的設(shè)計(jì)和實(shí)現(xiàn) ....................................................................26 設(shè)計(jì)思路 .......................................................................................................26 分頻器 fd127的源代碼 ...........................................................................26 異或門(mén) sxor 模塊的設(shè)計(jì)和實(shí)現(xiàn) .......................................................................27 設(shè)計(jì)思路 .......................................................................................................27 sxor 的源代碼 ...............................................................................28 本地 m 序列模塊的設(shè)計(jì)和實(shí)現(xiàn) .......................................................................29 第 6 章 Quartus II 對(duì)系統(tǒng)的仿真結(jié)果與分析 .................