【正文】 ................... 1 集成電路設(shè)計(jì)方法 ........................................................................................................... 2 FPGA 的設(shè)計(jì)流程 ............................................................................................................. 3 本文的目的和意義 ........................................................................................................... 4 ２ CPU架構(gòu)設(shè)計(jì) .......................................................................................................................... 5 計(jì)算機(jī)體系結(jié)構(gòu) ............................................................................................................... 5 CPU 的基本結(jié)構(gòu) ............................................................................................................... 6 CPU 的功能及模塊的劃分 ............................................................................................... 6 流水線設(shè)計(jì) ....................................................................................................................... 6 3 指令系統(tǒng)設(shè)計(jì) ............................................................................................................................. 8 指令系統(tǒng) ........................................................................................................................... 9 數(shù)據(jù)通路設(shè)計(jì) ................................................................................................................. 11 4 VHDL語(yǔ)言和 Quartus II........................................................................................................... 12 VHDL 語(yǔ)言概述 .............................................................................................................. 12 VHDL 的起源 ........................................................................................................ 12 VHDL 特點(diǎn) ............................................................................................................ 13 VHDL 的基本結(jié)構(gòu) .......................................................................................................... 13 QurtusII 開(kāi)發(fā)系統(tǒng) ........................................................................................................... 15 非常易使用的 EDA 設(shè)計(jì)軟件 ............................................................................. 15 Quartus II 設(shè)計(jì)流程 ............................................................................................... 16 5 CPU設(shè)計(jì)與仿真 ....................................................................................................................... 17 取指令段 ......................................................................................................................... 17 PC 選擇模塊的設(shè)計(jì) .............................................................................................. 18 程序計(jì)數(shù)器模塊的設(shè)計(jì) ....................................................................................... 20 程序計(jì)數(shù)器加 1 模塊的設(shè)計(jì) ............................................................................... 22 程序存儲(chǔ)器模塊的設(shè)計(jì) ....................................................................................... 22 流水線寄存器模塊的設(shè)計(jì) ................................................................................... 22 取指模塊的綜合設(shè)計(jì) ........................................................................................... 23 指令譯碼段 ..................................................................................................................... 24 譯碼段的功能描述 ............................................................................................... 25 符號(hào)擴(kuò)展模塊 ....................................................................................................... 25 寄存器文件模塊 ................................................................................................... 26 分支控制寄模塊 ................................................................................................... 27 ID/EX 段流水線寄存器 ........................................................................................ 28 指令譯碼段模塊的綜合設(shè)計(jì) ............................................................................... 29 基于 FPGA 的嵌入式 CPU 設(shè)計(jì) V 指令執(zhí)行段 ..................................................................................................................... 30 算術(shù)邏輯單元模塊的設(shè)計(jì) ................................................................................... 31 EX/MEM 段流水線寄存器模塊的設(shè)計(jì) ............................................................... 33 指令執(zhí)行段的綜合 ............................................................................................... 34 存儲(chǔ)器訪問(wèn)段 ................................................................................................................. 35 MEM/WB 段流水線寄存器模塊的設(shè)計(jì) .............................................................. 35 輸出端口寄存器模塊的設(shè)計(jì) ............................................................................... 36 多路數(shù)據(jù)選擇器模塊的設(shè)計(jì) ............................................................................... 36 MEM 段各模塊的綜合 ......................................................................................... 37 回寫(xiě)段 ............................................................................................................................. 38 流水線相關(guān)問(wèn)題處理 ..................................................................................................... 39 數(shù)據(jù)相關(guān)的問(wèn)題 ................................................................................................... 39 數(shù)據(jù)相關(guān)檢測(cè)模塊的設(shè)計(jì) ................................................................................... 39 數(shù)據(jù)前推模塊的設(shè)計(jì) ........................................................................................... 39 控制相關(guān)的處理 ................................................................................................... 40 結(jié)構(gòu)相關(guān)的處理 ................................................................................................... 41 控制單元 .....................................................