at89c51的介紹外文翻譯-其他專業(yè)-文庫吧資料
2025-01-27 06:19本頁面
【正文】 m Memory Lock Bits On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly. 2021屆電子信息科學(xué)與技術(shù)專業(yè)畢業(yè)設(shè)計(jì)外文翻 譯 4 set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALEdisable bit has no effect if the microcontroller is in external execution mode. PSEN Program Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12volt programming enable voltage (VPP) during Flash programming, for parts that require12volt VPP. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an onchip oscillator, as shown in Figure a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a dividebytwo flipflop, but minimum and 2021屆電子信息科學(xué)與技術(shù)專業(yè)畢業(yè)設(shè)計(jì)外文翻 譯 2 Port 0 Port 0 is an 8bit opendrain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs. Port 0 may also be configured to be the multiplexed address/data bus during accesses to external program and data memory. In this mode P0 has internal Pullup r
畢業(yè)設(shè)計(jì)相關(guān)推薦
鄂ICP備17016276號-1