【正文】 利用EDA工具，電子設(shè)計師可以從概念、算法、協(xié)議等。EDA技術(shù)就是以計算機為工具，設(shè)計者在EDA軟件平臺上，用硬件描述語言HDL完成設(shè)計文件，然后由計算機自動地完成邏輯編譯、化簡、分割、綜合、優(yōu)化、布局、布線和仿真，直至對于特定目標芯片的適配編譯、邏輯映射和編程下載等工作。這一切極大地改變了傳統(tǒng)的數(shù)字系統(tǒng)設(shè)計方法、設(shè)計過程和設(shè)計觀念，促進了EDA技術(shù)的迅速發(fā)展。在電子技術(shù)設(shè)計領(lǐng)域，可編程邏輯器件（如CPLD、FPGA）的應(yīng)用，已得到廣泛的普及，這些器件為數(shù)字系統(tǒng)的設(shè)計帶來了極大的靈活性。t need to consider a choice pletion the spare part of design first while designing a personnel to carry on a design with the VHDL, can concentrate energy to carry on design of excellent the design description plete after, can carry out its function with various different spare part structure. Very strong transplantation VHDL is a kind of hardware description for standardize language, the same of design description can be support by the different tool and make to design to describe of the transplantation make possible. Be easy to a share and reply to VHDL adoption can build up various mold piece that can again make use of according to the design method of canned in advance design or use to design a medium backup mold a piece before and depositted these to the database in, can be in laterly of the design carry on replying to use, can make the design result be design the personnel39。Since the support mold piece turns a design, support layer39。s tread electric circuit with random the design of electric circuit, this be the other hardware description although the language can39。s at the beginning e out by American Ministry of National Defense development to provide the American solider with the credibility which uses to raise a design with cut 1 kind of development period to use the scope smaller design language. VHDL,Translating into chinese is soon extremely high the description language of the integrated circuit it of the application mainly is an application in the design of numerical electric , it is in the application most in china is the design which uses in the FPGA/CPLD/ in some units with stronger real strenght, it is also use to design ASIC. The VHDL mainly useds for the structure, behavior which describes numerical system, function with addition to implying many languages sentence which have a hardware characteristic, VHDL languages forms and description style and sentence construction are very similar at general calculator deluxe procedure structure characteristics is an engineering design, or call that the design entity(can be a ponent, an electric circuit mold piece or a system) is divided into exterior(or call but part, and port) with inner part(or call to can39。s in 20 centuries, calculator assistance manufacturing, calculator assistance test and calculator lend support to the concept of engineering a development since EDA technique is to take calculator as tool, design at EDA software terrace up, use the hardware description language HDL pletion a design a document, then is of oneself pleted logic to edit and translate, turn Chien, partitioned by the calculator, prehensive, excellent turn, set up, cloth line with imitate really, until for particular target chip of proper go together with to edit and translate, the logic reflect to shoot with plait distance download etc. EDA technical emergence, biggest raised efficiency and maneuverability of electric circuit design, eased to design of labor strength. These spare parts can pass a software plait a distance but as to it39。s nation, has been being actively investigating a new design method of the electronics electric circuit, and carried on an exhaustive change in the aspects of designing a method, tool wait, obtain huge the design realm of the electronics technique, the application of programmable logic spare part(like CPLD, FPGA), have already got extensive universality, these spare parts brought tremendous vivid for the design of numerical spare parts can pass a software plait a distance but as to it39。參考文獻[1]潘松,:科學出版社,2005版.[2]:清華大學出版社,2005版.[3][M].重慶：重慶大學出版社，.[4]:西安電子科技大學出版社,2004版.[5]Pan Song Application foreground of CPLD/FPGA in electron design[J] Electon technology apply 1997,(7):1621.[6][M].北京：希望電子出版社，.[7]黃任,:北京航空航天大學出版社. 2005. [8]:機械工業(yè)出版社,2006版.[9][M].武漢:武漢理工大學出版社，.[10]Wei zhou, Zong qiang, Jian new development of precision frequency measurement techniquc[C], preceedings of the 1995 IEEE internitional frequency control symposium .P P. 354 35 9 , 1995.[11]潭會生,:西安電子科技大學出版社,2004版.[12]:西安電子科技大學出版社.[13][M].北京：中國科學文化出版社，.附錄A 英文文獻The development of EDA and the application of VHDL9039。 再次，要感謝在畢業(yè)設(shè)計過程中幫我提供研究資料的同學們，如果沒有他們的幫助，此次設(shè)計的完成將變得非常困難。這對我接下來能夠順利地完成設(shè)計工作起到了良好的鋪墊作用。每次在設(shè)計中遇到困難時，何老師都會幫助我解決一道道難題，并且鼓勵我要敢于想象敢于創(chuàng)新。 在這里首先要感謝我的導師何偉老師。致謝經(jīng)過一段時間的忙碌和學習，本次畢業(yè)設(shè)計已經(jīng)接近尾聲了。而且，VHDL語言對EDA技術(shù)產(chǎn)生的影響也是深遠的，他縮短了電子產(chǎn)品的設(shè)計周期，為設(shè)計者提供了方便。但由于經(jīng)驗上的不足，有些地方還需要做進一步地改善。程序中所用到得數(shù)據(jù)均可以根據(jù)實際情況進行設(shè)置，修改靈活方便。本設(shè)計在確立總體預期實現(xiàn)功能的前提下，分層次進行設(shè)計。分別用紅、黃、綠、藍等的不同組合來指揮兩個方向的通車與禁行，用數(shù)碼管作為倒計時指示，實時的控制當前交通燈時間使LED顯示器進行倒計時工作并與狀態(tài)燈保持同步，在保持交通安全的同時最大限度的提高交通順暢交替運行。同時給出了軟硬件設(shè)計方法。硬件驗證的實物圖見附錄C。通過驗證，交通燈的亮滅狀態(tài)與數(shù)碼管顯示倒計時時間一致，與設(shè)計原理相符合，基本上達到了一個交通指示燈的要求。 45s整體仿真圖5 硬件驗證首先選擇器件EPM7128SLC8415，使用ByteBlaste 下載電纜把項目以在線配置的方式下載到實驗箱的EPM7128SLC8415器件中，整個電路的標準1s信號有實驗箱上信號源提供，信號燈輸出部分AY、AL、AR、AG、BY、BL、BR、BG分別接到八個發(fā)光二極管上，從而可以顯示甲乙車道的紅綠燈亮滅的狀態(tài)。 45s譯碼模塊仿真圖(7)顯示控制模塊仿真結(jié)果：，乙路的60s紅燈的使能信號en60b為高電平，甲路的10s左拐燈得使能信號en10a為高電平，輸出由對應(yīng)的定時輸入數(shù)據(jù)得到，最后分別將數(shù)據(jù)輸出到譯碼電路。圖中ain4是譯碼前的BCD碼，dout7是輸出給7段數(shù)碼管的7為二進制數(shù)，由于采用的是共陰數(shù)碼管，所以輸出對應(yīng)位的1代表對應(yīng)段亮。 5s定時單元模塊仿真圖(5)60s定時單元仿真結(jié)果：，在整個電路中控制紅燈的亮滅，甲路的60s使能信號en60a為高電平，輸出根據(jù)時鐘信號計時，開始先清零，然后從60s開始倒計時輸出到顯示電路，表示甲路進行60s倒計時。 45s定時單元模塊仿真圖（3）10s定時單元仿真結(jié)果：，在整個電路中控制黃燈的亮滅，乙路的10s使能信號en10b為高電平，輸出根據(jù)時鐘信號計時，開始先清零，然后從10s開始倒計時輸出到顯示電路，表示乙路左拐進行10s倒計時。數(shù)碼管顯示94. 4 各模塊及整體仿真結(jié)果（1）交通燈控制模塊仿真結(jié)果：，當ag、al、ay、ar為高電平時代表甲路綠、左拐、黃燈依次按順序亮，此時乙路對應(yīng)br為高電平，也就是的紅燈亮；當甲路為紅燈，也就是ar為高電平時，乙路綠、左拐、黃燈依次按順序亮，也就是bg、by、bl依次為高電平。數(shù)碼管顯示7 when 1000=dout7=1111111。數(shù)碼管顯示5 when 0110=dout7=1111101。數(shù)碼管顯示3 when 0100=dout7=1100110。數(shù)碼管顯示1 when 0010=dout7=1011011。 when 0000=dout7=0111111。 輸入四位BCD碼 dout7:out std_logic_vector(6 downto 0))。 （5）譯碼顯示，將用于顯示BCD碼數(shù)據(jù)進行譯碼，將顯示控制輸出的四位二進制數(shù)送入譯碼器后顯示到共陰數(shù)碼管上。 then t3b=t3b+1。or en