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【正文】 圖形液晶顯示模塊使用手冊[Z]. 北京: 清華蓬遠(yuǎn)公司, 2000[11] （第三版）.北京：清華大學(xué)出版社，[12] 王建校. 51系列單片機(jī)及C51程序設(shè)計(jì)[M ]. 北京:科學(xué)出版社, 2002.[13] [M ].北京：機(jī)械工業(yè)出版社，2004.[14] 何立民,單片機(jī)應(yīng)用系統(tǒng)設(shè)計(jì),北京：航天航空大學(xué)出版社,2～5,46～50[15] 李廣弟,單片機(jī)基礎(chǔ),北京：北京航空航天大學(xué)出版社,2001,56～64[16] 何希才,新型實(shí)用電子電路400例,電子工業(yè)出版社,2000年,60～65[17] 張毅剛,彭喜元,新編MCS51單片機(jī)應(yīng)用設(shè)計(jì),第一版,哈爾濱工業(yè)大學(xué)出版社,2003,25～27,411～417[18] Wolf W, 孫玉芳等譯. 嵌入式計(jì)算系統(tǒng)設(shè)計(jì)原理. 北京: 機(jī)械工業(yè)出版社, 2002 [19] 鄭人杰. 計(jì)算機(jī)軟件測試技術(shù). 北京: 清華大學(xué)出版社, 1992 [20] 胡漢才. 單片機(jī)原理及系統(tǒng)設(shè)計(jì). 北京:清華大學(xué)出版社, 2002[21] ,Nenghaung sheng ,“A High purity High Speed Direct Digital Synthesizer”, AFCS,1995,207211[22] MC88100 RSIC Microprocessor User’s Manual (Second edition). Englewood Cliffs: Prentice Hall, 1990[23] Silicon Storage Technology Inc, SST39VF800A [24] Integrated Silicon Solution Inc. IS61LVI2816 [25] Texas Instruments Inc. TPS767D318 Datasheet. 1999 致 謝 附 錄AT24C01The AT24C01 provides 1024 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 128 words of 8 bits each. The device is optimized for use in many industrial and mercial applications where low power and low voltage operation are essential. The AT24C01 is available in space saving 8pin PDIP, 8pin TSSOP, and 8pin JEDEC SOIC packages and is accessed via a 2wire serial interface. In addition, the entire family is available in ( to ) and ( to ) versions. Block DiagramPin Description :SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin isopendrain driven and may be wireORed with any number of other opendrain or open collector Organization AT24C01, 1K SERIAL EEPROM: Internally organized with 128 pages of 1 byte 1K requires a 7bit data word address for random word addressing. Pin Capacitance:Applicable over remended operating range from TA =25176。C, f = MHz, VCC = +.DC Characteristics:Applicable over remended operating range from: TAI=40176。Cto+85176。C, VCC = + to +, TAC =0176。Cto+70176。C,VCC = + to + (unless otherwise noted). AC Characteristics:Applicable over remended operating range from TA =40176。Cto+85176。C, VCC = + to +, CL = 1 TTL Gate and100 pF (unless otherwise noted).Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer toData Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A hightolow transition of SDA with SCL high is a start conditionwhich must precede any other mand (refer to Start and Stop Definition timing diagram).STOP CONDITION: A lowtohigh transition of SDA with SCL high is a stop condition which terminates all munications. After a read sequence, the stop mand will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8bit words. Any device on the system bus receiving data (when municating with the EEPROM) must pull the SDA bus low to acknowledge that it has successfully received each word. This must happen during the ninth clock cycle after each word received and after all other system devices have freed the SDA bus. The EEPROM will likewise acknowledge by pulling SDA low after receiving each address or data word (refer to Acknowledge Response from Receiver timing diagram).STANDBY MODE: The AT24C01 features a low power standby mode which is enabled: (a) upon powerup and (b) after the receipt of the STOP bit and the pletion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2wire part can be reset by following these steps:(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then(c) create a start condition as SDA is high. Write Operations BYTE WRITE: Following a start condition, a write operation requires a 7bit data word address and a low write bit. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8bit data word. Following receipt of the 8bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internallytimed write cycle to the nonvolatile memory. All inputs are disabled during this write cycle , tWR, and the EEPROM will not respond until th
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