基于at89c51的led廣告顯示電路的設(shè)計(jì)畢業(yè)論文-資料下載頁(yè)
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【正文】 1,00H 。列制碼 MOV R4,96 。移動(dòng)“ ”及“單片機(jī)仿真”6個(gè)字符共96列CM: MOV R5,5 。每屏反復(fù)顯示5次 MOV R3,16 。列數(shù)C1: MOV R2,0 。取碼指針C16: MOV P0,00H MOV P2,00H 。關(guān)顯示 CLR MOV A,R2 MOVC A,@A+DPTR 。取當(dāng)前列顯示字碼的第一個(gè)字節(jié) MOV P0,A 。送1~8行控制口 INC R2 MOV A,R2 MOVC A,@A+DPTR 。取當(dāng)前列的顯示字碼的第二個(gè)字節(jié) MOV P2,A 。送9~15行控制口 INC R2 MOV P1,R1 。送列控制碼 INC R1 ACALL D1MS 。顯示2MS ACALL D1MS DJNZ R3,C16 。一屏16列是否顯示完 MOV R3,16 DJNZ R5,C1 。未顯示5次，繼續(xù) INC DPTR 。一屏反復(fù)顯示5次完，字碼表初值加2 INC DPTR DJNZ R4,CM 。96列未移動(dòng)完，繼續(xù) AJMP MAIN 。96列移動(dòng)完，返回，重新從“ ”開(kāi)始顯示D1MS: MOV R6,2 MOV R7,248 DJNZ R7,$ DJNZ R6,$4 RETTAB:DB 000H ,000H ,000H ,000H ,000H ,000H ,000H ,000H ,000H ,000H ,000H ,000H ,000H ,000H ,000H ,000H 。DB 000H ,000H ,000H ,000H ,000H ,000H ,000H ,000H ,000H ,000H ,000H ,000H ,000H ,000H ,000H ,000H 。 ,DB 000H ,000H ,000H ,008H ,000H ,008H ,0E0H ,008H ,0F4H ,00DH ,054H ,005H ,0F4H ,07FH ,0F8H ,07FH 。DB 01EH ,005H ,0FEH ,005H ,0FAH ,006H ,010H ,002H ,000H ,006H ,000H ,004H ,000H ,000H ,000H ,000H 。單,0DB 000H ,000H ,000H ,000H ,000H ,010H ,000H ,01CH ,0FCH ,00FH ,0FCH ,003H ,040H ,002H ,040H ,002H 。DB 07EH ,07FH ,03EH ,07FH ,020H ,000H ,020H ,000H ,000H ,000H ,000H ,000H ,000H ,000H ,000H ,000H 。片,1DB 000H ,008H ,040H ,00CH ,040H ,006H ,0DCH ,03FH ,0FEH ,03FH ,022H ,011H ,020H ,01DH ,0F0H ,00FH 。DB 0F0H ,003H ,0F0H ,00FH ,0F0H ,01FH ,010H ,010H ,000H ,01CH ,000H ,01CH ,000H ,010H ,000H ,000H 。機(jī),2DB 000H ,001H ,080H ,001H ,0C0H ,000H ,0F0H ,03FH ,0FCH ,03FH ,04CH ,018H ,040H ,00CH ,040H ,027H 。DB 0CCH ,063H ,0ECH ,079H ,028H ,01FH ,020H ,007H ,020H ,000H ,020H ,000H ,000H ,000H ,000H ,000H 。仿,3DB 000H ,000H ,000H ,010H ,000H ,098H ,000H ,0C8H ,0E8H ,06FH ,0E8H ,03FH ,07CH ,01BH ,07EH ,00AH 。DB 0E6H ,03FH ,0E4H ,07FH ,004H ,06CH ,000H ,004H ,000H ,004H ,000H ,000H ,000H ,000H ,000H ,000H 。真,4 END 外文資料SEQUENTIAL LOGIC DESIGNAbstract：The FLIPFLOP is a basic element of sequential logic FLOPs and binational logic circuits,any sequential logic circuit can be most important sequential circuits that are widely used in digital systems are registers and are discussed in detail in the following sections..The design of registers and counters using FLIPFLOPs has been introduced followed by standard MSI of the mon applications of registers and counters have also been discussed.The design methods for general clocked sequential circuits have also been . the system may be specified in terms of inputoutput relationship or/and the sequence of states to be followed when clock pulses are usual design steps are:reduction of states,state assignment and nextstate decoder design.The synchronous counter is a special case of the general clocked sequential circuit and can be designed using the design methods developed for clocked sequential circuits.Asynchronous sequential circuits do not use clock pulses and their response depends upon the sequence in which the input signal circuits use delay circuits as memory elements memory capability to these SR FLIPFLOPs fall under this category of delay ciruits which are extensively used in asynchronous sequential analysis and design of asynchronous sequential circuits have been discussed in detail.26
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