【正文】 提供了設(shè)計(jì)的主題思想，在設(shè)計(jì)過程中，她在自己的繁忙工作之余指導(dǎo)我們，檢查并排除了我們?cè)O(shè)計(jì)過程中的諸多漏洞。無論是軟件的使用，還是理論的運(yùn)用，我都有很大的收獲。在論文的編寫過程中，她給我提出寶貴的意見，并且給與細(xì)致的指導(dǎo)。最重要的是指導(dǎo)老師教會(huì)我們?cè)S多分析、解決問題的方法，這在書本中無法學(xué)到的，她的教誨培養(yǎng)了我科學(xué)的思維方法和一絲不茍的治學(xué)態(tài)度，淵博的學(xué)識(shí)更使我受益匪淺。 其次，我要感謝的是我的同伴——許震乾同學(xué)，本系統(tǒng)的設(shè)計(jì)由我們共同完成。在整個(gè)設(shè)計(jì)過程中，我們配合的非常默契，共同克服困難，出謀劃策。正是由于我們的努力，整個(gè)設(shè)計(jì)才能進(jìn)行的那么順利。 再次，我要感謝大學(xué)四年所有教過我的老師和我們的輔導(dǎo)員，感謝他們四年來對(duì)我的教誨和幫助?？萍嘉墨I(xiàn)：LPC2114/2124/2212/2214GENERAL DESCRIPTIONThe LPC2114/2124/2212/2214 are based on a 16/32 bit ARM7TDMISTM CPU with realtime emulation and embedded trace support, together with 128/256 kilobytes (kB) of embedded high speed flash memory. A 128bit wide internal memory interface and a unique accelerator architecture enable 32bit code execution at maximum clock rate. For critical code size applications, the alternative 16bit Thumb Mode reduces code by more than 30% with minimal performance penalty.With their apct 64 and 144 pin packages, low power consumption, various 32bit timers, bination of 4channel 10bit ADC or 8channel 10bit ADC (64 and 144 pin packages respectively), and up to 9 external interrupt pins these microcontrollers are particularly suitable for industrial control, medical systems, access control and pointofsale.Number of available GPIOs goes up to 46 in 64 pin package. In 144 pin packages number of available GPIOs tops 76 (with external memory in use) through 112 (singlechip application). Being equipped wide range of serial munications interfaces, they are also very well suited for munication gateways, protocol converters and embedded soft modems as well as many other generalpurpose applicationsARCHITECTURAL OVERVIEWThe LPC2114/2124/2212/2214 consists of an ARM7TDMIS CPU with emulation support, the ARM7 Local Bus for interface to onchip memory controllers, the AMBA Advanced Highperformance Bus (AHB) for interface to the interrupt controller, and the VLSI Peripheral Bus (VPB, a patible superset of ARM’s AMBA Advanced Peripheral Bus) for connection to onchip peripheral functions. The LPC2114/2124/2212/2214 configures the ARM7TDMIS processor in littleendian byte order.AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the 4 gigabyte ARM memory space. Each AHB peripheral is allocated a 16 kilobyte address space within the AHB address space. LPC2114/2124/2212/2214 peripheral functions (other than the interrupt controller) are connected to the VPB bus. The AHB to VPB bridge interfaces the VPB bus to the AHB bus. VPB peripherals are also allocated a 2 megabyte range of addresses, beginning at the gigabyte address point. Each VPB peripheral is allocated a 16 kilobyte address space within the VPB address space.The connection of onchip peripherals to device pins is controlled by a Pin Connection Block. This must be configured by software to fit specific application requirements for the use of peripheral functions and pins.LPC2114/2124/2212/2214 REGISTERSAccesses to registers in LPC2114/2124/2212/2214 is restricted in the following ways:1) user must NOT attempt to access any register locations not defined.2) Access to any defined register locations must be strictly for the functions for the registers.3) Register bits labeled ’’, ’0’ or ’1’ can ONLY be written and read as follows: ’’ MUST be written with ’0’, but can return any value when read (even if it was written with ’0’). It is a reserved bit and may be used in future derivatives. ’0’ MUST be written with ’0’, and will return a ’0’ when read. ’1’ MUST be written with ’1’, and will return a ’1’ when read.The following table shows all registers available in LPC2114/2124/2212/2214 microcontroller sorted according to the address.Access to the specific one can be categorized as either read/write, read only or write only (R/W, RO and WO respectively).Reset Value field refers to the data stored in used/accessible bits only. It does not include reserved bits content. Some registers may contain undetermined data upon reset. In this case, reset value is categorized as undefined. Classification as NA is used in case reset value is not applicable. Some registers in RTC are not affected by the chip reset. Their reset value is marked as * and these registers must be initialized by software if the RTC is enabled.Registers in LPC2114/2124/2212/2214 are 8, 16 or 32 bits wide. For 8 bit registers shown in Table 2, bit residing in the MSB (The Most Significant Bit) column corresponds to the bit 7 of that register, while bit in the LSB (The Least Significant Bit) column corresponds to the bit 0 of the same register.If a register is 16/32 bit wide, the bit residing in the top left corner of its description, is the bit corresponding to the bit 15/31 of the register, while the bit in the bottom right corner corresponds to bit 0 of this register.Examples: bit ENA6 in PWMPCR register (address 0xE001404C) represents the bit at position 14 in this register。 bits 15, 8, 7 and 0 in the same register are reserved. Bit Stop on MR6 in PWMMCR register (0xE0014014) corresponds to the bit at position 20。 bits 31 to 21 of the same register are reserved.Unused (reserved) bits are marked with and represented as gray fields. Access to them is restricted as already described.PREFETCH ABORT AND DATA ABORT EXCEPTIONSThe LPC2114/2124/2212/2214 generates the appropriate bus cycle abort exception if an access is attempted for an address that is in a reserved or unassigned address region. The regions are:? Areas of the memory map that are not implemented for a specific ARM derivative. For the LPC2114/2124/2212/2214, this is: Address space between OnChip NonVolatile Memory and OnChip SRAM, For 128 kB Flash device, this is memory address range from 0x0002 0000 to 0x3FFF FFFF, while for 256 kB Flash device this range is from 0x0004 0000 to 0x3FFF FFFF. Address space between OnChip Static RAM and External Memory. This is an address range from 0x4000 3FFF to 0x7FFF DFFF.For these areas, both attempt