【正文】 aximum available I/O number is 180 , 404 and 512, have been developed respectively. The 180I/O FPGA has a pintopin input delay and pintopin output delay or less. This paper was based on a 1P5M standard CMOS technology process, and on a design technology of custom layout. The primary technology parameters of the FPGA family products acplish the foreign advanced level of kindred products. New idea of our research subject was a new I/O cicuit structure by using the SRAM array design to realize insystem programmable and the characters of analog cicuit structure can reduce the chip area and give higher performance. The 180I/O FPGA chip with ceramic packages solved the problem that there were no military devices in foreign kindred products and satisfied the requirement of ABSTRACT IV important military engineering. This product has been finished the layout designs of the FPGA series were pleted and were ahead of the schedule of plan. The products were used and approbated by many customer, we broke the forbiddance for the devices by foreign countries, and contributed that the key device can be established in China for our army. Keywords: FPGA Dynamicconfiguration I/O Multistandards 5Vtolerance Weakkeeper目 錄 V 目 錄 第一章 緒 論 ...................................................... 1 課題的背景和意義 ................................................. 1 現(xiàn)場(chǎng)可編程門陣列簡(jiǎn)介 ........................................ 2 SRAM 編程技術(shù)介紹 .......................................... 3 FPGA 和 ASIC 的對(duì)比 ......................................... 4 市場(chǎng)需求分析 ................................................ 6 國(guó)內(nèi)外研究現(xiàn)狀與發(fā)展趨勢(shì) ......................................... 7 國(guó)外研究現(xiàn)狀 ................................................ 7 國(guó)內(nèi)研究現(xiàn)狀 ............................................... 12 未來(lái)發(fā)展趨勢(shì) ............................................... 13 主要內(nèi)容、創(chuàng)新及論文安排 ........................................ 13 第二章 FPGA 多標(biāo)準(zhǔn)兼容可編程 I/O 相關(guān)技術(shù)研究 ..................... 16 架構(gòu)技術(shù)研究 .................................................... 16 學(xué)術(shù) FPGA 架構(gòu)技術(shù)研究 ..................................... 16 FPGA 算法研究 .......................................... 16 FPGA 整體架構(gòu)研究 ...................................... 17 商業(yè) FPGA 架構(gòu)技術(shù)研究 ..................................... 19 Xilinx 公司 FPGA 架構(gòu) .................................... 19 Altera 公司 FPGA 架構(gòu) .................................... 20 各類 FPGA 架構(gòu)分析 ...................................... 21 多標(biāo)準(zhǔn)兼容可編程 I/O 技術(shù)研究 .................................... 21 電平接口標(biāo)準(zhǔn)研究 ........................................... 21 專業(yè)術(shù)語(yǔ) ................................................ 22 接口標(biāo)準(zhǔn)分類 ............................................ 22 目 錄 VI CMOS I/O 設(shè)計(jì)技術(shù)研究 ...................................... 27 CPLD 編程 I/O 技術(shù)研究 ...................................... 28 CPLD 可編程 I/O 設(shè)計(jì)技術(shù) ................................. 28 CPLD I/O 輸出 skew 控制設(shè)計(jì)技術(shù) .......................... 28 FPGA 可編程 I/O 技術(shù)研究 .................................... 30 FPGA 可編程 I/O 技術(shù)研究 ................................. 30 FPGA 中可編程 I/O 的分類 ................................. 31 可編程技術(shù) I/O 比較 .......................................... 31 第三章 FPGA 多標(biāo)準(zhǔn)兼容可編程 I/O 設(shè)計(jì)與驗(yàn)證 ....................... 32 設(shè)計(jì)技術(shù)參數(shù)和設(shè)計(jì)要求 .......................................... 32 設(shè)計(jì)要求 ................................................... 32 設(shè)計(jì)技術(shù)參數(shù) ............................................... 35 FPGA 可編程標(biāo)準(zhǔn) I/O 設(shè)計(jì) ........................................ 36 總體結(jié)構(gòu) ................................................... 36 設(shè)計(jì)原理和設(shè)計(jì)方法 ......................................... 38 輸出緩沖器 .............................................. 39 輸入緩沖器 .............................................. 41 I/O BANK 介紹 ........................................... 44 FPGA 可編程非標(biāo)準(zhǔn) I/O 設(shè)計(jì) ...................................... 45 全 局時(shí)鐘輸入管腳 ........................................... 45 配置控制信號(hào)輸入管腳 ....................................... 47 配置控制信號(hào)輸出管腳 ....................................... 48 FPGA 可編 程標(biāo)準(zhǔn) I/O 核心電路設(shè)計(jì) ................................ 48 輸出數(shù)據(jù)通路設(shè)計(jì) ........................................... 48 輸出數(shù)據(jù)選擇控制單元 UIO_OUTMUX ...................... 48 輸出數(shù)據(jù)緩沖器單元 UIO_OUTBUF ......................... 50 輸入數(shù)據(jù)通路設(shè)計(jì) ........................................... 64 輸入緩沖器單元設(shè)計(jì) UIO_INBUF ........................... 64 輸入數(shù)據(jù)閾值損失補(bǔ)償單元 UIO_REFIN ..................... 71 可編程延遲與輸入通道選擇模塊 ............................ 75 目 錄 VII I/O 工作模式控制與配置單元設(shè)計(jì) .............................. 77 配置信息存儲(chǔ)與選擇單元設(shè)計(jì) .............................. 77 I/O 工作模式控制單元設(shè)計(jì) ................................. 79 邊界掃描鏈與輸入輸出寄存器單元設(shè)計(jì) ......................... 81 輸入輸出保護(hù)與 PCI 接口標(biāo)準(zhǔn)控制電路 ......................... 85 5V 容許保護(hù)電路 ......................................... 85 weak keeper 數(shù)據(jù)保持單元 ................................. 91 上拉和下拉電阻 .......................................... 93 多標(biāo)準(zhǔn)兼容非標(biāo)準(zhǔn) I/O 接口核心電路設(shè)計(jì) ........................... 93 全局時(shí)鐘輸入 I/O 單元設(shè)計(jì) ..................................... 93 時(shí)鐘輸入緩沖器單元 AGCK_IN ............................. 94 配置點(diǎn)存儲(chǔ)單元模塊 ARRSRAM_DOWN .................... 96 邊界掃描單元模塊 BSCAN_B .............................. 97 全局輸入時(shí)鐘延遲補(bǔ)償模塊 GCLK_COMPENSATION ......... 97 配置控制信號(hào)輸入管腳 ....................................... 104 配置控制信號(hào)輸出管腳 ....................................... 105 多標(biāo)準(zhǔn) I/O 接口電路的擴(kuò)展 ...................................... 106 LVDS 接口標(biāo)準(zhǔn)介紹 ......................................... 106 電路實(shí)現(xiàn)原理 .............................................. 108 定制版圖設(shè)計(jì) .................................................. 108 整體電路功能與參數(shù)仿真 ........................................ 109 第四章 FPGA 電源與時(shí)鐘系統(tǒng)研究與設(shè)計(jì) ............................112 DLL 電源系統(tǒng)設(shè)計(jì) ............................................. 112