【正文】 選用的12MHz晶振的計數(shù)周期如下式所示：圖34 時鐘電路單片機的復(fù)位引腳RST為單片機提供了初始化手段。當(dāng)振蕩器復(fù)位器件時，要保持RST腳兩個機器周期的高電平時間。并行I/O口：并行I/O接口的數(shù)據(jù)所有的位同時傳輸?shù)?，其特點是速度快、效率高，但是傳輸多少位就需要多少根線，因此成本較高，適合于動態(tài)顯示的應(yīng)用。隨著INTEL i960系列特別是后來的ARM系列的廣泛應(yīng)用，32位單片機迅速取代16位單片機的高端地位，并且進入主流市場。單片機的P1口控制矩陣鍵盤。 顯示器件選擇方案一：采用LCD液晶顯示屏，液晶顯示屏的顯示功能強大，可顯示大量文字、圖形，顯示多樣，清晰可見，但是價格昂貴，需要的接口線多。在搶答期間，數(shù)碼管可以顯示搶答定時時間，搶答成功以LED燈亮提示，如果選手搶答犯規(guī)，則以另一色LED燈亮提示。因其功耗低，超高型，低成本，功能完整，在國內(nèi)越來越受到用戶的重視和廣泛使用。 選題目的及意義搶答器是一種應(yīng)用于企事業(yè)單位或者智力競賽節(jié)目中作為搶答使用的一種電子設(shè)備。圖 21 系統(tǒng)設(shè)計方框圖 設(shè)計方案選擇 系統(tǒng)設(shè)計方案選擇方案一：利用邏輯電路來搭建系統(tǒng)電路。方案二：采用點陣式數(shù)碼管顯示，點陣式數(shù)碼管是由八行八列的發(fā)光二極管組成，比較適合顯示文字或者制作大型屏幕。本設(shè)計采用4*4矩陣鍵盤，S1S8按鍵分別代表8個選手的按鍵。而傳統(tǒng)的8位單片機的性能也得到了飛速提高，處理能力比起80年代提高了數(shù)百倍。AT89S51是美國ATMEL公司生產(chǎn)的低電壓、高性能的CMOS 8位單片機，AT89S51的內(nèi)部結(jié)構(gòu)：MCS51系列單片機都是在8051的基礎(chǔ)上增加部分資源，例如程序存儲器、數(shù)據(jù)存儲器、I/O口、定時器/計數(shù)器及一些其他特殊部件構(gòu)成的，其一般都含有8051除程序存儲器外的其他基本硬件。ALE：地址鎖存控制信號。復(fù)位是單片機的初始化操作，在本設(shè)計中復(fù)位電路采用按鍵電平方式，使RST引腳經(jīng)過10u電解電容與VCC電源接通，同時經(jīng)過電阻與地連接而實現(xiàn)，單片機是高電平復(fù)位有效，當(dāng)按鍵S16按下時候，單片機的9腳RESET管腳處于高電平，此時單片機處于復(fù)位狀態(tài)。74LS164將輸入的串行數(shù)據(jù)鎖存在并行輸出端，通過這些并行口線驅(qū)動數(shù)碼管的各字段。從而達到所要求的功能。在開發(fā)大型軟件時更能體現(xiàn)高級語言的優(yōu)勢。 程序設(shè)計流程 本設(shè)計軟件設(shè)計流程圖如圖41所示，完整源程序見附錄5。動態(tài)顯示驅(qū)動：數(shù)碼管動態(tài)顯示方式是將所有的段選線并聯(lián)在一起，由一個8位I/O口來控制，再利用單片機的其他I/O口來作為數(shù)碼管的位選線。 j=j1。即TX端口有從“1”到“0”的負(fù)跳變，計數(shù)器就自動加1，計算機是在每個機器周期采樣為0時，計數(shù)器即加一計數(shù)，計算機需用兩個機器周期來識別1次計數(shù)，因而最大計數(shù)速率為振蕩頻率的1/24。T1被允許計數(shù)后，從初值開始加1計數(shù)。第五章 系統(tǒng)調(diào)試故障與分析系統(tǒng)調(diào)試包括硬件調(diào)試和軟件調(diào)試。 對于模塊結(jié)構(gòu)程序，要對子程序逐個進行調(diào)試。在具體操作中用戶系統(tǒng)在開發(fā)系統(tǒng)環(huán)境的下，先借用仿真器的CPU，存儲器等資源進行工作。在以后的學(xué)習(xí)生活中我將不忘老師的嚴(yán)謹(jǐn)?shù)闹螌W(xué)態(tài)度和工作精神，以老師為榜樣，認(rèn)真踏實地工作，不辜負(fù)老師的期望。 P1端口是一個帶內(nèi)部上拉電阻的8位雙向I /O端口。端口引腳 第二功能RXD(串行輸入端口) TXD(串行輸出端口) INT0(外部中斷0) INT1（外部中斷1） T0(定時/計數(shù)器0外部輸入） T1（定時/計數(shù)器1外部輸入） WR（外部數(shù)據(jù)存儲器寫選通） RD（外部數(shù)據(jù)存儲器讀選通）3. 存儲器結(jié)構(gòu)MCS51單片機內(nèi)核采用程序存儲器和數(shù)據(jù)存儲器空間分開的結(jié)構(gòu)，均具有64KB外部程序和數(shù)據(jù)的尋址空間。uchar BCD_TAB[11]={0X84,0XE7,0X2C,0X25,0X47,0X15,0X14,0XA7,0X04,0X05,0XFF}。 for(i=0。 delay(50)。i8。 flag=0。 //選手4 } else { rong_cal=rong_calamp。 write__call2_164(rong_cal)。 case 72:break。 case 34:if(flag==1) { write__call1_164(0xfb)。 write__call2_164(rong_cal)。 //選手2 } else { rong_cal=rong_calamp。 if((jamp。 } } write_164(0xff)。i++) { CLK_164=0。uchar good_cal。在AT89S51 ，如果EA連接到電源+（VCC） ，程序首先執(zhí)行地址從0000H到FFFH內(nèi)部存儲器，在執(zhí)行地址從1000H到FFFFH的外部程序存儲器。對端口寫“1”，通過內(nèi)部的上拉電阻把端口拉到高電平，此時可作為輸入口。參考文獻[1] 張友德，趙志英，、應(yīng)用與實驗[M].復(fù)旦大學(xué)出版社,2004.[2] ，2011年25期.[3] .[4] 徐軼林，.[5] （自然科學(xué)版）.2009年25卷12期.[6] .[7] 薛頂柱，（自然科學(xué)版）.2010年29卷5期.[8] ，2008年04期.[9] ，2009年28期.[10] 康麗杰，.[11] 眭碧霞，SUI .[12]附錄1 電路原理圖附錄2 中英文翻譯英文部分：The Description of AT89S511. General DescriptionThe AT89S51 is a lowpower, highperformance CMOS 8bit microcontroller with 4K bytes of InSystem Programmable Flash memory. The device is manufactured using Atmel’s highdensity nonvolatile memory technology and is patible with the industrystandard 80C51 instruction set and pinout. The onchip Flash allows the program memory to be reprogrammed insystem or by a conventional nonvolatile memory programmer. By bining a versatile 8bit CPU with InSystem Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highlyflexible and costeffective solution to many embedded control applications.The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16bit timer/counters, a fivevector twolevel interrupt architecture, a full duplex serial port, onchip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Powerdown mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.2 .PortsPort 0 is an 8bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs. Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pullups are required during program verification.Port 1 is an 8bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the loworder address bytes during Flash programming and verification.Port PinAlternate FunctionsMOSI (used for InSystem Programming)MOSO (used for InSystem Programming) SCK(used for InSystem Programming)Port 2 is an 8bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that use 16bit addresses (MOVX DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the highorder addres